中文 English

Week In Review: Auto, Security, Pervasive Computing

Synopsys’ ASIL D compliant processor IP; Arm’s functional safety GPU, CPU, ISP.

popularity

Security
Synopsys’ Cybersecurity Research Center disclosed that its research resulted in three Common Vulnerability and Exposures (CVE) advisories on wireless router chipsets that have partial authentication bypass vulnerabilities. The vulnerability lets an attacker send an unencrypted data frame through a WPA2-protected WLAN, which will may respond with an encrypted data frame that the attacker can mine for or change the data. CVE-2019-18989 warns that the issue was found in Mediatek’s MT7620N chipset; CVE-2019-18990 shows it in Realtek RTL8812AR 1.21WW, RTL8196D 1.0.0, RTL8192ER 2.10, and RTL8881AN 1.09 devices; and CVE-2019-18991 shows it in Qualcomm’s Atheros AR9132 3.60 (AMX.8), AR9283 1.85, and AR9285 1.0.0.12NA devices. Synopsys says in a press release that Mediatek and Realtek are offering patches upon request and Qualcomm said the chipsets have been discontinued and current chipsets are unaffected by the vulnerability. The CVE is list of numbered vulnerabilities produced by the United States’ NIST’s National Vulnerabilities Database.

Automotive
Processor IP from Synopsys has now been certified for full ISO 26262 ASIL D compliance, based on SGS-TÜV Saar’s assessment. ASIL D compliance means the DesignWare ARC EM22FS functional safety processor IP meets random hardware fault detection and systematic functional safety development flow requirements. The IP has error-correcting code (ECC) for memories and interfaces, transient fault protection for internal registers, diagnostic error injection, and an integrated self-checking safety monitor.

Arm unveiled IP for autonomous systems in automotive and industrial markets. The IP is focused on safety, of different levels, for different use cases. The Cortex-A78AE is Arm’s highest performance CPU with safety, Arm Mali-G78AE is Arm’s first functional safety GPU, and Arm Mali-C71AE image signal processor (ISP) designed for vision use cases in safety-critical situations. The GPU has a new a partitioning system with up to four partitions so it can run different workloads separately with safety-related workloads on dedicated partitions with no contention for GPU resources and assured performance on-demand. The ISP, which supports data from up four real-time cameras and 16 memory streams, has features for ASIL B / SIL2 safety capability. It can be used in automotive ADAS and industrial robotics where humans are working near robots. The CPU can support features needed for applications up to ASIL D / SIL 3. With an upgrade to the split-lock architecture, the CPU has temporal diversity to guard against common cause failures. A hybrid mode makes it possible to target lower ASIL levels while running DSU-AE logic in lock mode. Also, the first of planned security features in the CPU is the Pointer Authentication (PAC), to protect against shoring up vulnerabilities in return-oriented-programming.

5G
Picocom is using Moortec’s in-chip sensing fabric to monitor dynamic conditions in its SoC for 5G small cell infrastructure. Picocom’s distributed unit (DU) baseband offload SoC is designed to be deployed in cityscapes and buildings to increase 5G coverage and reduce the processing load on 5G macro cells under the Open RAN initiative, according to a press release. Picocom specializes in 5G Open RAN baseband semiconductors and software.

5G laptops R&D is being fueled by Ansys’ simulation. Compal Electronics is adding 5G millimeter wave antenna module to laptop. Compal worked with Ansys to shorten the time needed for electromagnetic simulation and automated analysis of the data. Compal already has an U.S. FCC certification for its 5G laptop, which comes out this year, according to a press release.

Pervasive computing
AI startup Groq started shipping its hardware for data centers, the Groq node, equipped with its Tensor Streaming Processor (TSP) chip. Marvell’s ASIC IP went into the Groq’s TSP chip, which enabled Groq to focus on its AI architecture. The Groq node holds eight Groq cards in a single chassis and nodes can be clustered. Each node has 6 PetaOPs of performance, according to Groq’s press release, and yet consuming only 3.3KW of power in a 5U form factor. The TSP is also being shipped on Groq’s PCIe card. The processor is made on Globalfoundries’ 14nm. Groq current works mostly in customers in fintech, autonomous vehicles, and government labs.

Military/aerospace
China unveiled a large rocket for crewed misisons to the moon. SpaceX scrapped a launch 18 seconds before blastoff on October 1 because of a ground-based sensor reading. The launch payload is 60 Starlink internet satellites, set to join SpaceX’s Starlink megaconstellation in orbit to beam down internet service to underserved areas. The Starlink network is already being used by first responders in the United States. CNBC reports that first responders in Washington state are already taking advantage of the network, using it to restore internet service in wildfire areas. A separate SpaceX launch is due to go up on Friday, October 2. Northrop Grumman also aborted a launch of an Antares rocket with 4 tons of NASA supplies for the International Space Station (ISS) because of first a trespassing boat and then an “unknown problem” with a ground support equipment. The launch may be attempted again tonight.

Seven private companies that are building commercial space stations — and that are not run by Elon Musk — are highlighted by Nanalyze.

The Space Foundation, a Colorado-based 501(c)(3) global space advocate, inducted three technologies first developed for use in space into its Space Technology Hall of Fame. The 2020 three technologies are:

October 8th will be the official ceremony, according to a press release.

People & Companies
Arteris IP
, known network on chip (NOC) interconnect IP, will acquire the assets and team members of Magillem Design Services. Arteris IP says it will become an SoC assembly company. “As we integrate our technologies to accelerate and simplify the SoC assembly design flow, we will enhance innovation in both SoC IP integration software and the highly configurable on-chip interconnect IP that implements chip architectures,” said K. Charles Janac, Arteris IP’s president and CEO, in a press release.

Job, Event and Webinar Boards: Find industry jobs and upcoming conferences and webinars all in one place on Semiconductor Engineering. Knowledge Center: Boost your semiconductor industry knowledge. Videos: See the latest Semiconductor Engineering videos.



Leave a Reply


(Note: This name will be displayed publicly)