Author's Latest Posts

High-Quality Silicon With Cloud-Based Verification

New materials, vertically stacked architectures, and angstrom-level process technologies—the complexity of today’s SoCs continues to grow to meet the needs of demanding applications such as AI, autonomous vehicles, and high-performance computing. This trend only places greater pressure on verification, already notorious for being a significant bottleneck in chip development. Design teams... » read more

The Road To Osmosis

It’s happening. Some may have speculated that, with the acquisition of OneSpin by Siemens, the OneSpin user group meeting, more commonly known as Osmosis, would be formally (pun intended) absorbed into a larger Siemens event. Well, I’m here to tell you that Osmosis is officially on the books and will continue to focus on the specific area of formal verification. The team has been working di... » read more

Deep Dive Into Hardware Security Verification At This Year’s Osmosis User Group

We’ve been talking for months about how to successfully verify designs to avoid security weaknesses and vulnerabilities. In the upcoming Osmosis (OneSpin Meeting on Solution, Innovation & Strategy) user group event, attendees will get to hear first-hand from one of our most ardent users how they were able to secure their hardware design. The two-day, virtual event on November 3rd and 4... » read more

The Early Bird Gets More Secure Hardware

I’m sure you’ve heard the expression “The early bird gets the worm.” This proverb emphasizes the importance of starting something early to maximize the potential outcome. In terms of hardware security, this idiom is spot on. Cybersecurity shouldn’t only be about protecting the software from attacks. Hardware is just as important. Cyberattacks continue to advance significantly, prog... » read more

Easing The Burden Of Early Bug Detection

Integrated circuit designers are under constant pressure to deliver bug free code that meets ever more rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design proce... » read more

Formally Verifying SystemC/C++ Designs

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Precision: A Case Study For Success

Recently, I was watching a documentary on the NASA Perseverance mission to Mars. I’ve always been fascinated by space travel and the engineering efforts to make it happen. We’ve all heard that the landing for this trip to Mars was the most precise in history, but what the documentary brought to light is the precision involved in each and every aspect of the Perseverance Rover design and dev... » read more

The Case For FPGA Equivalence Checking

Formal Equivalence Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized code. In the Field Programmable Gate Array (FPGA) space, EC is still a relatively new concept, but is rapidly becoming important given the large devices being employed today. For the largest FP... » read more

Verification Knowledge At Your Fingertips

If you’re like most engineers, you’re curious about how other engineers tackle some of the most difficult challenges. What can you absorb from them and apply to your own projects? Learning from experience has tremendous value but learning from others’ experiences is arguably more valuable since the cost to acquire that knowledge is significantly cheaper. At OneSpin, we’ve lowered... » read more

RISC-V Becoming Less Risky With The Right Verification

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the ... » read more

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