Week In Review: IoT, Security, Autos


The United States signed trade agreements with the China (phase one agreement) and North American countries Mexico and Canada this week. The SIA (Semiconductor Industry Association), which represents the U.S. semiconductor industry, applauded the agreements. Still to be worked out is the second part, or phase two, of the U.S.’s agreement with China. AI/Edge M&A Apple is acquiring edge... » read more

RISC-V Markets, Security And Growth Prospects


Semiconductor Engineering sat down to discuss open instruction set hardware with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.  Part one of this discussion is ... » read more

Open ISAs Gaining Traction


Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

What Is A Custom Processor?


Spurred by the latest cyclical development boom, the semiconductor industry is entering a new golden era of custom processors, but this time ‘custom processor’ means something different. A generation ago, every major semiconductor company had in-house processors: SuperH, PowerPC, V800, Alpha, MEP, Trimedia, etc., with some specializing more than others for particular domains. But industr... » read more

A Holistic View Of RISC-V Verification


Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and sys... » read more

Enabling The RISC-V Ecosystem


Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more apparent that RISC-V is fundamentally changing system-on-chip (SoC) development. Dozens of commercial and open... » read more

Complete Formal Verification of RISC V Processor IPs for Trojan-Free Trusted ICs


RISC-V processor IPs are increasingly being integrated into system-on-chip designs for a variety of applications. However, there is still a lack of dedicated functional verification solutions supporting high-integrity, trusted integrated circuits. This paper examines an efficient, novel, formal-based RISC-V processor verification methodology. The RISC-V ISA is formalized in a set of Operational... » read more

The 7nm Pileup


The number of 7nm designs is exploding. Cadence alone reports 80 new 7nm chips under design. So why now, and what does this all mean? First of all, 7nm appears to be the next 28nm. It's a major node, and it intersects with a number of broad trends that are happening across the industry, all of which involve AI in one way or another. The big question now is how many of them will survive long ... » read more

Designing An AI SoC


Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

The Challenge Of RISC-V Compliance


The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

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