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Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)


A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

RISC-V Is Thriving: Here’s What You Need to Know


RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify each individual instruction given to the computer. As RISC-V is an open standard, anyone can implement, customize, and expand the ISA to suit their r... » read more

5 Good Things About RISC-V


RISC-V has been around for some time now, and if you are here it’s because you have heard of it. But perhaps you still need to be convinced that it is the future? If you still wonder about its potential and benefits, here are five good things about RISC-V. 1. RISC-V is an open standard Let’s start simple. This is nothing new, but let’s be clear on what open standard means. Open stan... » read more

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases


This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

Customizing Processors


The design, verification, and implementation of a processor is the core competence of some companies, but others just want to whip up a small processor as quickly and cheaply as possible. What tools and options exist? Processors range from very small, simple cores that are deeply embedded into products to those operating at the highest possible clock speeds and throughputs in data centers. I... » read more

Big Changes In Embedded Software


Every good hardware or software design starts with a structured approach throughout the design cycle, but as chip architectures and applications begin focusing on specific domains and include some version of AI, that structure is becoming more difficult to define. Embedded software, which in the past was written for very narrow functions with a minimal footprint, is increasingly getting blended... » read more

Why RISC-V Is Succeeding


There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

How To Extend The ‘Unscalable’ RISC Architectures


A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable.  This blog was really quite interesting and made some very good points about the limitations of a pure RISC design. The limitations of a pure RISC design It takes me back: some of my first marketing tasks were around the religious war between RISC ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Synopsys and 3D virtual-environment company Dassault Systèmes are collaborating on an automotive lighting system development platform. Synopsys’ optical design tools — LucidShape, LightTools, and CODE V — will be integrated with Dassault Systèmes' 3DEXPERIENCE Platform, which is used by automotive teams from different disciplines to work together on designs and simulations. ... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences


Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

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