tag: ISA

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases
By Technical Paper Link - 18 Aug, 2022 - Comments: 0

This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

Customizing Processors
By Brian Bailey - 28 Jul, 2022 - Comments: 1

The design, verification, and implementation of a processor is the core competence of some companies, but others just want to whip up a small processor as quickly and cheaply as possible. What tools and options exist? Processors range from very small, simple cores that are deeply embedded into products to those operating at the highest possible clock speeds and throughputs in data centers. I... » read more

Big Changes In Embedded Software
By Ann Mutschler - 28 Apr, 2022 - Comments: 0

Every good hardware or software design starts with a structured approach throughout the design cycle, but as chip architectures and applications begin focusing on specific domains and include some version of AI, that structure is becoming more difficult to define. Embedded software, which in the past was written for very narrow functions with a minimal footprint, is increasingly getting blended... » read more

Why RISC-V Is Succeeding
By Brian Bailey - 24 Feb, 2022 - Comments: 5

There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

How To Extend The ‘Unscalable’ RISC Architectures
By Rupert Baines - 24 Feb, 2022 - Comments: 0

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable.  This blog was really quite interesting and made some very good points about the limitations of a pure RISC design. The limitations of a pure RISC design It takes me back: some of my first marketing tasks were around the religious war between RISC ... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 15 Oct, 2021 - Comments: 0

Automotive Synopsys and 3D virtual-environment company Dassault Systèmes are collaborating on an automotive lighting system development platform. Synopsys’ optical design tools — LucidShape, LightTools, and CODE V — will be integrated with Dassault Systèmes' 3DEXPERIENCE Platform, which is used by automotive teams from different disciplines to work together on designs and simulations. ... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences
By Various Writers - 13 Oct, 2021 - Comments: 0

Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Working With RISC-V
By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

Is RISC-V The Future?
By Roddy Urquhart - 29 Jul, 2021 - Comments: 4

Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is RISC-V going to be the dominant ISA in the processor market?’ This is certainly an unfolding situation and has changed significantly in the last five years. RISC-V originated at the University of California, Berkeley, in 2010 and took a number of years to get traction with industry. A bi... » read more

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