Author's Latest Posts

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences

Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Generalized Class-E Power Amplifier With Shunt Capacitance And Shunt Filter

This paper presents a generalized analysis of the Class-E power amplifier (PA) with a shunt capacitance and a shunt filter, leading to a revelation of a unique design flexibility that can be exploited either to extend the maximum operating frequency of the PA or to allow the use of larger active devices with higher power handling capability. The proposed PA fulfills zero voltage switching (ZVS)... » read more

Semiconductor Industry Association Factbook, 2019

You may already know that semiconductors make possible the global trillion dollar electronics industry. But did you know that worldwide sales have increased at a compound annual rate of almost 7 percent per year since 1998? To find out more—including why it is critical for policymakers to enact measures that boost growth and promote innovation—download the 2019 SIA Factbook. The 2019 ... » read more

Power Management Techniques For Smart Grid Devices

Energy efficiency is a top concern among developers building connected devices for the smart grid. Initially, the application-centric approach to building a device was used. But today, with sophisticated hardware power management features available on most modern processors, this is no longer the case. What’s needed is an OS-level approach that allows developers to take advantage of the full ... » read more

big.LITTLE Technology: The Future of Mobile

With the evolution from the first mobile phones through smartphones to today’s superphones and tablets, the demand for compute performance in mobile devices has grown at an incredible rate. Today’s devices need to service smarter and more complex interactions, such as voice and gesture control, combined with seamless and reliable content delivery. Gaming and user interfaces have also grown ... » read more

System-Aware SoC Power, Noise And Reliability Sign-off

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Model Extraction And Circuit Simulation Approaches For Successful SSO Analysis Of Chip-Package-Board Systems

This paper concerns guidelines to support successful SSO analysis for Chip-Package- Board systems. The procedures detailed address extraction and circuit simulation application of high node-count (N>100) frequency domain models. The focus of this paper is the low frequency portion, including DC, of the spectrum for broadband S- parameters. Frequency domain model extraction options and transient... » read more

Ultra Low Power Integrated Platform For Connectivity And Audio/Voice/Sensing

A look at an integrated approach on a single DSP and why it's needed. To download this white paper, click here. » read more

Memory Power Reduction In SoC Designs Using PowerPro MG

Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50% to 70% of the power dissipation. We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories. To ... » read more

Formal Verification Of Power-Aware Designs Using JasperGold Low Power Verification App

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, th... » read more

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