A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform


It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

SOC Design & IP Management—A Must For Functional Verification


As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

Why IP Quality Is So Difficult To Determine


Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

Adding Order And Structure To Verification


You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal


Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. In addition, participants had to prove that... » read more

When Correct Is Not Enough: Formal Verification of Fault-Tolerant Hardware


Once upon a time, hardware functional verification was all about ensuring that a circuit would perform its specified functions under all legal input stimuli. Today, though, gaining confidence that a hardware design is correct is often not enough. Several industries, including automotive, medical, and aerospace, rely on safety-critical hardware to keep people safe. Other systems, for example, in... » read more

Portable Test and Stimulus Standard Version 1.0


The definition of the language syntax, C++ library API, and accompanying semantics for the specification of verification intent and behaviors reusable across multiple target platforms and allowing for the automation of test generation is provided. This standard provides a declarative environment designed for abstract behavioral description using actions, their inputs, outputs, and resource depe... » read more

Domain Crossing Nightmares


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Auto Chip Design, Test Changes Ahead


The automotive industry’s unceasing demand for performance, coupled with larger and more complex processors, are driving broad changes in how electronics are designed, verified and tested. What's changing is that these systems, which include AI-oriented logic developed at the most advanced process nodes, need to last several times longer than traditional IT and consumer devices, and they n... » read more

Verdi Transaction Debug Platform


Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

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