Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs


A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

Glitch Power Issues Grow At Advanced Nodes


An estimated 20% to 40% of total power is being wasted due to glitch in some of the most advanced and complex chip designs, and at this point there is no single best approach for how and when to address it, and mixed information about how effective those solutions can be. Glitch power is not a new phenomenon. DSP architects and design engineers are well-versed in the power wasted by long, sl... » read more

The Limits Of AI-Generated Models


In several recent stories, the subject of models has come up, and one recurrent theme is that AI may be able to help us generate models of a required abstraction. While this may be true in some cases, it is very dangerous in others. If we generalize, AI should be good for any model where the results are predominantly continuous, but discontinuities create problems. Unless those are found and... » read more

A Survey Of Machine Learning Applications In Functional Verification


Functional verification is computationally and data-intensive by nature, making it a natural target of machine learning applications. This paper provides a comprehensive and up-to-date analysis of FV problems addressable by ML. Among the various ML techniques and algorithms, several emerging ones have demonstrated outstanding potential in FV. Yet despite the promising research results, criti... » read more

New Technology Accelerates Multi-Die System Simulation


AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

The True Cost Of Software Changes


Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

Welcome To EDA 4.0 And The AI-Driven Revolution


By Dan Yu, Harry Foster, and Tom Fitzpatrick Welcome to the era of EDA 4.0, where we are witnessing a revolutionary transformation in electronic design automation driven by the power of artificial intelligence. The history of EDA can be delineated into distinct periods marked by significant technological advancements that have propelled faster design iterations, improved productivity, and fu... » read more

Can ML Help Verification? Maybe


Functional verification produces an enormous amount of data that could be used to train a machine learning system, but it's not always clear which data is useful or whether it can help. The challenge with ML is understanding when and where to use it, and how to integrate it with other tools and approaches. With a big enough hammer, it is tempting to call everything a nail, and just throwing ... » read more

Is AI Improving A Broken Process?


Verification is fundamentally comparing two models, each derived independently, to find out if there are any different behaviors expressed between the two models. One of those models represents the intended design, and the other is part of the testbench. In an ideal flow, the design model would be derived from the specification, and each stage of the design process would be adding other deta... » read more

Shifting The Design Paradigm To Improve Verification Efficiency


We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

← Older posts