An outline of open standards and methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters.
The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse, and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification. This paper outlines open standards and methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters.
Key aspects include:
Based on examples from several popular open-source cores, the talk associated with the paper provides guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.
Embedded World 2023 Conference Paper.
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