tag: coverage

ASIC Prototyping — New Design Realities Demand A New Approach
By Siemens EDA - 14 May, 2026 - Comments: 0

Modern ASIC design pushes prototypes to model vast RTL interactions across many FPGAs, often under high-bandwidth conditions that strain traditional systems. Verification teams also need fluid movement between emulation and at-speed prototyping, exposing any gaps in flow, tooling, or model continuity. This white paper presents an integrated solution that addresses these challenges through a uni... » read more

Leveraging Agentic AI Techniques to Improve Formal Verification (Infineon, et al.)
By Technical Paper Link - 28 Apr, 2026 - Comments: 0

A new technical paper, "Agentic AI-based Coverage Closure for Formal Verification," was published by researchers at Infineon and the NIT Jalandhar. Abstract "Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines.... » read more

Why Proof Convergence Matters
By Ed Sperling - 20 Apr, 2026 - Comments: 0

Achieving a deterministic "yes or no" answer in semiconductor verification is becoming more challenging as chip complexity increases. There are more cores, more potential interactions, and more reliance on AI to build AI chips. Ashish Darbari, CEO of Axiomise, talks about the impact of functional interactions involving safety and security, and where to look for common patterns to prevent bugs f... » read more

The Verification Conundrum
By Brian Bailey - 02 Feb, 2026 - Comments: 2

When constrained random test pattern generation became the de facto way to verify designs, reference models became necessary to check that a design was producing the correct output. These were often distributed across several models, such as checkers, scoreboards and assertions. Another model that had to be created was the coverage model. It was required because you had to know if a generate... » read more

RTL Signoff vs. Functional Signoff: What’s The Difference?
By Bradley Geden - 17 Jul, 2025 - Comments: 1

By Bradley Geden and Manoz Palaparthi In semiconductor design, “signoff” is often treated as a single milestone. In practice, however, it encompasses distinct verification phases with unique objectives. Functional signoff and RTL signoff represent two such phases. Both are essential, and each one is focused on different facets of correctness. While functional signoff verifies whether ... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

How To Optimize Silicon Utilization To Improve PPA
By Ashish Darbari - 29 Apr, 2025 - Comments: 0

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce ... » read more

The Price Of Fear
By Brian Bailey - 27 Feb, 2025 - Comments: 0

In my last blog, I talked about how pain is important when making predictions in the semiconductor industry. Pain is related to time to market and risk, and the flip side of risk is fear. Fear is one of the main drivers for a large number of EDA tools, such as those related to verification. The fear is taping out a chip, then waiting for what seems like an eternity to get the first chips bac... » read more

Maximizing Coverage Metrics with Formal Unreachability Analysis
By Synopsys - 25 Sep, 2024 - Comments: 0

Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

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