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Extending RISC-V ISA With Custom Instruction Set Extension


RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used. One of the groups is special; it has no predefined instruct... » read more

How to Connect Questa VIP to the Processor Verification Flow


Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more