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Author's Latest Posts


Semiconductor Scaling Is Failing — What Next For Processors?


This in-depth paper looks at the changing dynamics in the semiconductor industry. In other words, why many companies are looking to customize their processor designs to keep pace with software and system demands. It goes onto highlight the opportunities available to companies of all sizes, in seeking to differentiate and specialize their processor designs. Click here to read more. » read more

Embedded AI On L-Series Cores


Over the last few years there has been an important shift from cloud-level to device-level AI processing. The ability to run AI/ML tasks becomes a must-have when selecting an SoC or MCU for IoT and IIoT applications. Embedded devices are typically resource-constrained, making it difficult to run AI algorithms on embedded platforms. This paper looks at what could make it easier from a softwar... » read more

What You Should Consider When Choosing A Processor IP Core


Most integrated circuits include at least one processor core and some embedded software. In the case of more complex systems-on-chip (SoC), there may be application processors running the main software, and operating system plus multiple specialised subsystems handling functions such as communications, security, and sensors. Requirements for processing vary considerably and there is a wide choi... » read more

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing


This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to co... » read more

Mythic Case Study


Mythic, the provider of a unique AI compute platform, was designing an innovative intelligence processing unit (IPU) and found themselves in need of a small, power-efficient, yet programmable core to take care of specific supporting functions. As no off-the-shelf core would exactly match the needs and customization proved challenging, Mythic eventually opted for a complete solution by Codasip. ... » read more

Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions


When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage. Traditionally, such cores have been in distinct categor... » read more

Better Benchmarks Through Compiler Optimizations: Codasip Jump Threading


The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark. An interesting observation regarding these test suites is that the performance numbers continue to improve for a given architecture, even... » read more

Extending RISC-V ISA With Custom Instruction Set Extension


RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used. One of the groups is special; it has no predefined instruct... » read more

How to Connect Questa VIP to the Processor Verification Flow


Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more