Enabling post-silicon customization with RISC-V.
RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain algorithms or application domains, for example DSP, AI/ML, and others, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or differentiation. These new instructions are usually added when the processor itself is designed, so it cannot be changed after tape-out.
In this paper, Codasip and Menta present a new approach that goes over this limitation and allows customization after tape-out, where architects can customize processors in the field. This can be achieved by using an eFPGA solution, enabling hardware reconfigurability in the field. The eFPGA IP is integrated inside Codasip RISC-V processors, in the pipeline.
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