Reconfigurable AI Building Blocks For SoCs And MCUs


FPGA chips are in use in many AI applications today, including Cloud datacenters. Embedded FPGA (eFPGA) is now becoming used for AI applications as well. Our first public customer doing AI with EFLX eFPGA is Harvard University, who will present a paper at Hot Chips August 20th on Edge AI processing using EFLX: "A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devi... » read more

FPGAs Drive Deeper Into Cars


FPGAs are reaching deeper and wider inside of automobiles, playing an increasingly important role across more systems within a vehicle as the electronic content continues to grow. The role of FPGAs in automotive cameras and sensors is already well established. But they also are winning sockets inside of a raft of new technologies, ranging from the AI systems that will become the central logi... » read more

Embedded FPGA Design Considerations


Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

Week In Review: Design, Low Power


M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

The Week In Review: Design


Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

Hardware Acceleration With eFPGAs


If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors –– then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more useful component in the tool box, available for decades and ... » read more

Architects: How To Get The Most Out Of eFPGA


At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA. 1. Use as little eFPGA a... » read more

FPGAs Becoming More SoC-Like


FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This family of devices now includes everything from basic programmable logic all the way up to complex SoC devices.... » read more

New Deep Learning Processors, Embedded FPGA Technologies, SoC Design Solutions


Some of the most valuable events at DAC are the IP Track sessions, which give small and midsize companies a chance to share innovations that might not get much attention elsewhere. The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market clearly was growing even faster than EDA itself, due to the fact that more and more chip mak... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

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