tag: eFPGA

The Next Generation Of Embedded FPGA
By Geoff Tate - 03 Aug, 2023 - Comments: 0

EFLX eFPGA has been in use in SoCs for more than 5 years, hardware and software. More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA. As we have worked with customers our architecture has evolved from EFLX Gen 1.0 to Gen 2.0, 2.1, 2.2, 2.3 and now in 2023 ... » read more

Fully Reconfigurable DSP: As Fast As Hardwired At ~2x Area/Power
By Jeremy Roberson - 01 Jun, 2023 - Comments: 0

Today if you want high performance DSP you have three choices: Hardwire your function – zero flexibility Use DSP IP based on VLIW Use FPGAs with DSP MACs or math engines What we hear from customers is that there is a growing need for very fast and very flexible DSP, which hardwired solutions can’t address. And that the fastest solutions are FPGAs, but they are big, high pow... » read more

Modular FPGA Makes FPGA Easier To Use
By Flex Logix - 31 May, 2023 - Comments: 0

Traditionally FPGAs are configured once at boot/power-on. This is because they almost always store the configuration file in a Flash memory which is updated from time to time (like your smart phone’s OS and apps). But eFPGA is in your SoC, so you can provide the configuration files from on chip SRAM, on chip NVM and/or off chip DRAM. EFLX eFPGA is reconfigurable. Process nodes like 40nm... » read more

Improving Image Resolution At The Edge
By Ed Sperling - 30 May, 2023 - Comments: 0

How much cameras see depends on how accurately the images are rendered and classified. The higher the resolution, the greater the accuracy. But higher resolution also requires significantly more computation, and it requires flexibility in the design to be able to adapt to new algorithms and network models. Jeremy Roberson, technical director and software architect for AI/ML at Flex Logix, talks... » read more

Issues And Challenges In Super-Resolution Object Detection And Recognition
By Jeremy Roberson - 04 May, 2023 - Comments: 0

If you want high performance AI inference, such as Super-Resolution Object Detection and Recognition, in your SoC the challenge is to find a solution that can meet your needs and constraints. You need inference IP that can run the model you want at high accuracy. You need inference IP that can run the model at the frame rate you want: higher frame rate = lower latency, more time for dec... » read more

Connect To Any Chip With Programmable GPIO
By Geoff Tate - 06 Apr, 2023 - Comments: 0

Your MCU/SoC today may have several options for GPIO connections: UART, SPI, I2C. But there are dozens of variations and kinds of GPIO interface protocols: you don’t have enough pins to provide all of them as hardwired options. As a result, a significant number of your customers either can’t use your chip because they need to connect to another with a GPIO interface you don’t support, ... » read more

The Importance Of Metal Stack Compatibility For Semi IP
By Geoff Tate - 02 Mar, 2023 - Comments: 0

Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks. Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more. The most complex, high performance chips, including performance FPGAs, typically use AL... » read more

Micro FPGAs And Embedded FPGAs
By Geoff Tate - 02 Feb, 2023 - Comments: 0

When people hear “FPGA” they think “big, expensive, power hungry.”  But it doesn’t need to be that way. Renesas has announced their Forge FPGA family. Details are at their website and in one of the many articles that covered their press release. Forge FPGAs show that FPGAs don’t have to be big, power hungry, and expensive. Forge FPGAs are tiny, draw standby current measure... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility
By Geoff Tate - 05 Jan, 2023 - Comments: 0

Systems companies like FPGA because it gives parallel processing performance that can outdo processors for many workloads and because it can be reconfigured when standards, algorithms, protocols or customer requirements change. But FPGAs are big, burn a lot of power and are expensive. Customers would like to integrate them into their adjacent SoC if possible. Dozens of customers are now u... » read more

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