Author's Latest Posts


PCIe Low-Power Validation Challenges And Potential Solutions


As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe


Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges


In PCI Express (PCIe), a high-speed serial computer expansion bus standard, Compliance mode is used for testing the transmitter and interconnect to assess if their voltage and timing are compliant with the specification. This testing happens in the Polling Compliance state which is a dedicated state for Compliance testing in the Link Training and Status State Machine (LTSSM). In Unraveling the... » read more