The complexities surrounding the verification of an Ethernet subsystem that integrates MACsec at Ethernet nodes of 800G (and beyond).
Ethernet is the interconnect technology of choice for a wide range of applications including (but not limited to) data centers, wireless backhaul, automotive, artificial intelligence (AI), and many other use cases. It is ubiquitous. As bandwidth requirements continue to scale to ever-dizzying heights due to the proliferation of data-intensive applications, developing, integrating, and validating Ethernet in SoC devices is becoming increasingly challenging. This white paper will explore the complexities surrounding the verification of an Ethernet subsystem that integrates MACsec and touch on the challenges of achieving first-time right silicon at current Ethernet nodes of 800G (and beyond). In addition, it will explore the collaboration of Rianta Solutions Inc. (“Rianta”) and Cadence to build the verification system with Rianta design IP and Cadence Verification IP (VIP).
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