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The Week In Review: Design


M&A CEVA bought RivieraWaves, which makes IP for WiFi and Bluetooth connectivity. CEVA said the deal will boost its market to 35 billion connected devices within six years. The two companies have been collaborating in the WiFi market for the past couple of years. Total cost of the deal is $19 million. Mentor Graphics acquired XS Embedded GmbH, a German-based developer of automotive-read... » read more

Which IP Is Better?


As the amount of third-party and re-used IP in a semiconductor increases, so do the number of questions about which possible IP choices perform better, use the least power, or work best with other components. So far, there is no simple way to make that choice. In most cases, this is simply splitting hairs. For all the IP that goes into designs, the bulk of it is chosen based on how often has... » read more

HDMI 2.0 Design And Verification Challenges


HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

Experts At The Table: Debug


By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Blog Review: Oct. 9


By Ed Sperling Mentor’s Simon Favre raises an interesting question: Why are 450mm wafers and EUV lithography related? The answer may surprise you. In his second broadcast, Cadence’s Brian Fuller interviews Gary Smith about where EDA will grow, why industry consolidation is a myth and why there is a dearth of reliable information about the electronics industry. Synopsys’ Mick Posner... » read more

Blog Review: Aug. 21


By Ed Sperling Mentor’s Michael Ford recalls the worst meetings in the world—ones that involve materials in the manufacturing process. Unfortunately there were a lot of them, so they were more like working in a recurring nightmare. Paging Freddie Krueger. Synopsys’ Karen Bartleson talks with Angisys CEO Anupam Bakshi about why EDA companies need to collaborate, and what’s the risk ... » read more

The Week In Review: Aug. 12


By Mark LaPedus Is the sky falling on semi capital spending? “We have seen several 2014 industry demand estimates in the 20%+ range, based on the ramps of FinFET and 3D NAND,” said Weston Twigg, an analyst with Pacific Crest Securities. “We expect Samsung to ramp spending in Q4, but we believe foundry and logic spending will remain soft for several quarters. As a result, we are developin... » read more

Software Debug Gets Tricky


By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

The Week In Review: June 21


By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Managing Functional Verification Projects


The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

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