What can go wrong in complex SoCs and how to find the problems.
Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use.
Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?
DARPA and a number of major vendors are backing this modular approach, but hurdles remain.
It’s been an uneven path leading to the current state of AI, and there’s still a lot of work ahead.
Assessing the reliability of a device requires adding more physical factors into the analysis, many of which are interconnected in complex ways.
Overall market will grow, but there are still pockets of uncertainty involving memory, scaling and tariffs.
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.
What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.
What happens when companies are combined? The outcome often isn’t as good as the announcement.
Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.
As complexity and device sizes rise, so does the need for an on-chip network.
Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.
Experts at the Table, part 1: While the Cloud may be ready for EDA, it is not clear how ready EDA is for the Cloud. What needs to change?
Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.
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