An Overview Of CXL Mode Alternate Protocol Negotiation


The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is th... » read more

Rethinking Chip Economics


As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m... » read more

Massive IoT Interop Fuels Protocol Battle


Wireless standards are plentiful, but most are not capable of being scaled to the level of a smart city. As a result, such networks have been built application-by-application using proprietary stacks, often with non-interoperable network layers. That, in turn, has slowed the proliferation of dense wireless connectivity at scale. “In a hyper-connected world, connectivity choices are driv... » read more

Battle Brewing Over Automotive Display Protocols


Displays are multiplying in new and future automobiles. That means a lot more display data moving around the vehicle and traveling some distance between sensor and processor. While existing protocols can handle some of the new duties, new protocols also are being developed specifically for this application. “Automotive displays are proliferating, increasing in numbers and in pixel densi... » read more

Heterogeneous Cache Coherence Requires A Common Internal Protocol


Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

Performance Increasingly Tied To I/O


Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

Executive Insight: K. Charles Janac


K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

Power, Standards And The IoT


Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

A Primer For The 802.XX Physical Layer


This is the second installment of the 802.XX for the IoE series of articles. The first one was published in the August issue and addressed the Media Access Control (MAC) layer. In this article, we will examine the elements of the physical (PHY) layer of the 802.11 protocol stack. For reference, the protocol stack is shown in figure 1. The best designs, like everything else, are built on a so... » read more

Tech Talk: SoC Protocol Debug


Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use. [youtube vid=AaY_AmdjUpo] » read more

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