Cracking The Mixed-Signal Verification Code


Rapid digitization in IoT, automotive, industrial, and communication industry segments are fueling semiconductor industry growth. This growth follows the “More than Moore” paradigm, where new design starts are spread across mature to advanced manufacturing nodes based on end-application targets. With this digitalization, data has become the most valuable resource. Mixed-signal designs pl... » read more

Simplifying Mixed-Signal Verification With The Symphony Platform


As complexity of mixed-signal SoCs grows, verification engineers cannot rely on the “divide and conquer” approach of verifying digital and analog blocks individually and then stitching them together for full-chip verification. Verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the subsystem to make sure there are no functional erro... » read more

Week In Review: Design, Low Power


M&A SMIT Holdings acquired S2C, a provider of FPGA prototyping hardware and software as well as interfaces and accessories, for $19 million, plus up to US$2 million in milestone based payments to the key management team. S2C was founded in 2003. SMIT, based in Hong Kong, makes pay TV broadcasting access and mobile point-of-sale payment systems for the Chinese market. Tools & IP Syn... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs


With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

Lab-To-Fab Testing


Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

Dynamic Fault Injection For System-Level Simulation Of MEMS


In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but numerically efficient models for the MEMS element. Simulations based on SystemC and SystemC AMS are suitable to analyze the nominal behavior of complex sys- tems including electronics... » read more

More Sigmas In Auto Chips


The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Searching For A System Abstraction


Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

Is It Time To Take Inductance And Electromagnetic Effects On SoCs Seriously?


Electromagnetic (EM) crosstalk impact on SoC performance has been a topic of discussion for a number of years, but how seriously have designers put EM crosstalk detection and avoidance into their SoC design practice? With increasing demand for faster bandwidth, lower power and higher density electronic systems, isn’t it about time to take inductance and EM effects seriously? This topic will b... » read more

Why All Nodes Won’t Work


A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

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