Timing Signoff Methodology For eFPGA

An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells.

The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the interface timing of the eFPGA does not change regardless of its internal configuration. It would look exactly like integrating, say, a RAM block.

Within the eFPGA, timing is determined by tools provided by the eFPGA supplier.

There are two methods of constructing eFPGA arrays:

1. Standard Cells – Flex Logix and Menta and others
2. Full Custom design – Achronix and others

An eFPGA is a very complex structure for determining timing. The logic is programmable and the interconnect is programmable. Any LUT’s output can be routed to any LUT’s input. If there are, say, 10,000 LUTs in an eFPGA, each LUT can have connections to 10,000 other LUTs for a total of 100 Million possible connections! For any given RTL, of course, only a small subset of these possible connections is actually formed, but any of these connections can be used in another configuration.

To make this manageable, the timing is broken down into stages. The path from one LUT to another LUT consists of multiple interconnect segments: going from the output of a LUT to one switch then another switch then another switch, etc., until eventually reaching the input of another LUT.

Timing has to be characterized for every interconnect segment, and every input/output relationship of every switch, so the timing can be built up for a path.

Even in a relatively small eFPGA of 10,000 LUTs, there are well over 100,000 interconnect segments and switches to time.

In a full custom design, SPICE simulations have to be done for all of the segments for each voltage/temperature/process combination desired – a very significant computing task.

In a standard cell eFPGA design, things are much easier and more reliable. The timing signoff is done, for TSMC designs, using TSMC cell timing libraries and TSMC-qualified library extraction flows for cell delays, along with TSMC-qualified wire-RC extraction flows (QRC, StarRC) for interconnect delays, and TSMC-qualified timing signoff flows (PrimeTime/Tempus).

For cell models, it should include:

• CCS-NP.lib (Composite Current Source, Noise/Power aware liberty model) for standard cells
• AOCV models for on-chip variation
• Path-based propagation for most accurate cell delay and slew propagation

For wire models (T16FF+/FFC):

• RCworst Ccworst T (worst-case RC, worst-case double-patterning coupling, temperature-aware model) for SSGNP -40/125C corner
• RCbest Ccbest T (best-case RC, best-case double-patterning coupling, temperature-aware model) for FFGNP -40/125C corner
• RCtpical for TT 85C corner
• Noise-SI delay characterized for worst-case aggressor/victim scenario (1GHz, all clocks active)

SDF (standard delay format) files are generated from these signoff quality, TSMC qualified cell and wire models. Using Primetime/Tempus, the SDF file is generated giving timing information for all corners for all standard cells and all interconnect segments in the eFPGA array.

In the case of Flex Logix EFLX eFPGA, since tiles are used, the SDF files are done at a tile level, accounting for all intra-tile and inter-tile wire segments. The SDF file is then used to create an EFLX interconnect delay model that scales to all array sizes from 1×1 up to the maximum allowable size (7×7 or larger). For other standard cell eFPGAs the files must be extracted at the full array level, requiring much more compute time.

Using this approach the eFPGA timing is of the same quality and accuracy as the customer’s ASIC signoff flows.

Further, the eFPGA timing models are validated against actual silicon to further confirm accuracy, as was recently done with the TSMC16FFC EFLX4K Logic and DSP cores in a 7×7 array posted now on TSMC OnLine.