tag: timing

Clocked DDR5 Client Memory Modules Enable Scaling To 9600 MT/s For AI PCs
By Carlos Weissenberg - 11 Jun, 2026 - Comments: 0

AI PCs are driving a new class of client workloads that behave very differently from traditional productivity or multimedia applications. Agentic AI systems are expected to plan, execute, and adapt in real time, maintaining persistent context while orchestrating multiple concurrent tasks. These usage patterns place sustained pressure on the memory subsystem, requiring not only higher peak bandw... » read more

Ensuring AI Reliability: Mitigating Silent Data Corruption Risks
By Noam Brousard - 12 May, 2026 - Comments: 0

Silent Data Corruption (SDC) is an industry challenge affecting data centers worldwide with increasing frequency. This phenomenon stems from untraceable hardware failures that make detection notoriously difficult. SDCs don’t leave any record in system logs or trigger exception mechanisms. The corrupted data they produce can propagate unnoticed, causing cascading failures that often demand ext... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression
By James Chuang - 13 Nov, 2025 - Comments: 0

Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

Improving IC System Quality And Performance
By Ed Sperling - 12 Nov, 2025 - Comments: 0

Ensuring that multi-die assemblies and advanced SoCs will work as expected from time zero to the end of their lifecycle adds new challenges for chipmakers and their customers. Chips are being run harder, hotter, and for longer periods of time, often in unique configurations and with customized workloads. Alex Burlak, vice president of test and analytics at proteanTecs, talks about how to identi... » read more

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

STA Strategies For Fast And Efficient Signoff Performance For Multi-Billion Instance Designs
By Manoz Palaparthi - 31 Jul, 2025 - Comments: 0

Contemporary AI, high-performance computing (HPC), mobile, and automotive designs continue to grow in size and complexity, putting a strain on the high-capacity compute required for static timing analysis (STA) workloads. Designs continue to grow at an unprecedented rate in size and complexity, outpacing the capacity of existing high-performance compute servers. A modern STA solution that can h... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML
By Alex Burlak - 10 Jun, 2025 - Comments: 0

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

Static Timing Analysis: Cell Delay Vs. Cell Drive Strength
By Pamula Sai Srinivas - 13 Mar, 2025 - Comments: 0

Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI circuit operation is very similar. If the driving cell is strong, it takes less delay and changes the output quicker than a weaker driver, which produces a sluggish response and takes longer t... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis
By Vinod Khera - 30 Jan, 2025 - Comments: 0

Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

From Reaction To Prevention In Data Center RAS
By Noam Brousard - 15 Oct, 2024 - Comments: 0

The rise of artificial intelligence (AI), cloud services, and IoT has fueled the rapid expansion of hyperscale data centers. These massive facilities house thousands of servers, all working to support an increasingly digital world. But as the scale of data centers grows, so too does the need for reliable and high-performance semiconductors. Semiconductor failures and inconsistencies can cause s... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy