Will FPGAs Work As Expected?


OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs. https://youtu.be/RFlP2Z_-Yqs » read more

“Good Enough For Government Work?” Not Anymore.


When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as 40 years. To get an idea of how many people I’m talking about, there was a retirement party for at least 3 or 4 people every week just in our division. You can imagine tha... » read more

Aging Effects


Tech Talk: Fraunhofer EAS' group manager for quality and reliability, Andre Lange, talks about how to model aging effects and why the problems are becoming more difficult at advanced nodes. https://youtu.be/XHWww2PE7aY » read more

5nm Design Progress


Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

The Week In Review: Design


Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

Beyond Signoff


The future of connectivity is very promising - the new era of semiconductors will give rise to transformational products that will enable seamless connectivity with 5G, smarter devices with AI, next generation mobility with autonomous vehicles and immersive experiences with AR and VR. These cutting-edge electronics systems will require the use of advanced sub-16nm SoCs and complex packaging tec... » read more

Near-Threshold Issues Deepen


Complex issues stemming from near-threshold computing, where the operating voltage and threshold voltage are very close together, are becoming more common at each new node. In fact, there are reports that the top five mobile chip companies, all with chips at 10/7nm, have had performance failures traced back to process variation and timing issues. Once a rather esoteric design technique, near... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Tech Talk: eFPGA Timing


Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

The Week In Review: Design


M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

← Older posts