Lower Process Nodes Drive Timing Signoff Software Evolution


A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

The Challenge Of Balancing Performance And Accuracy For Advanced Node Timing Signoff


As process nodes shrink, complexity, cost and overall risk expand. Process variability that once was once acceptable now becomes a critical item as operating voltage decreases. Simply adding design margin makes the chip non-competitive. Physical effects that were once ignored now become critical as well. The impact of interconnect can no longer be modeled based on simple circuit topology. Layou... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution


A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

3 Types Of AI Hardware


As AI chips become more pervasive, three primary approaches are moving to the forefront. Bradley Geden, director of product marketing at Synopsys, looks at how to take advantage of repeatability, what the different flavors look like, the difference between flat and hierarchical design, and what impact black-box arrays have on programmability. » read more

Navigating Timing Margins Like Waze


Remember the pre-smartphone days, before navigation apps had our backs? Thanks to a lack of real-time visibility, ‘arriving early’ was the go-to strategy to avoid arriving late. Factor in too much ‘holdup time’ and you’d arrive a little too early. There’s nothing worse than nervously burning off an excess 30 minutes over a coffee you really didn’t need. Today you wouldn’t ... » read more

Timing Closure At 7/5nm


Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Timing Library LVF Validation For Production Design Flows


Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Where Timing And Voltage Intersect


João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Big Design, IP and End Market Shifts In 2020


EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

Advanced Features Of High-Speed Digital I/O Devices: Timing


In digital communication, timing is the most essential element. Any kind of violation to timing could cause you to transmit or receive incorrect data. As instruments and communication rates get faster, timing becomes even more vital, as even the smallest of changes in edges (in the pico-second range), could cause incorrect tests and communication failures. In the following paragraphs, discover ... » read more

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