Why Using Commercial Chiplets Is So Difficult

Security, reliability, and integration issues are slowing the market for plug-and-play tiles.


Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of that discussion, which was held in front of a live audience at the recent Design Automation Conference. Part one of this discussion is here. Part two is here.

[L-R] Ed Sperling, moderator; Mark Kuemerle, Marvell; Craig Bishop, Deca Technologies; Tony Mastroianni, Siemens EDA; Saif Alam, Movellus. Source: Semiconductor Engineering/Jesse Allen
[L-R] Ed Sperling, Mark Kuemerle, Craig Bishop, Tony Mastroianni, Saif Alam. Source: Jesse Allen/Semiconductor Engineering

SE: When you’re using an older chiplet and it’s updated, the timing may change because you’re mixing and matching a bunch of different elements. Can flexibility be built into them to avoid any problems, and does that add a lot of overhead?

Alam: Depending on the protocol interfaces, you may be able to isolate the problem. But if you break up the problem into pieces, you have a chiplet timing problem and then you have another bigger problem.

Bishop: As long as the UCIe timing works, at least they can talk to each other.

Mastroianni: It’s the same on the board. They have multiple chips, they’re coming from different places, and you connect them together.

SE: Do we need different methodologies for chiplets?

Kuemerle: We do, and we need to continue making improvements in methodologies. Multi-chip verification is not a slam dunk. You have to do a lot of thinking about how these chips are going to behave when they’re connected together. We can solve some of the hierarchical timing problems with chiplets, but when we lump together more and more content, we make the verification even more challenging. Verification probably needs work. As we move to 3D integration, I haven’t seen tools that will allow us to seamlessly integrate multiple layers of silicon together and figure out things like power delivery. None of that stuff has been fully vetted yet.

Bishop: On methodology side, tools are there for a lot of the design, layout, and system level. Flows are working. One area where I’ve seen quite a few questions recently is test. It’s not DFT. When I’m going through my assembly flow, for example, I have a bunch of chiplets coming from all different sources. Some of those chiplets cost a lot more than others. And I may have all known-good-die initially, because I tested them upfront. But that’s not enough when you’re putting them together chiplets in a system. I have to test those after they’ve been integrated together so that, ‘Hey, these links between all four of these chiplets actually work as intended.’ When I do this, do I put all my chips down on my chiplet and PHY integration and test after that? With some chiplet technologies, you can put some of your chiplets down first, make sure that works, then commit the expensive things, like an HBM stack. I might have 10 of those, and I want to make sure I test my multi-die system before I commit.

SE: It’s not trivial to change methodologies. You basically have to reorganize your company and break down some of the silos, which is a mammoth effort. That’s one of the reasons companies resist change, right?

Mastroianni: Yes, but the compelling advantages are there. However, there’s no free lunch.

SE: How do chiplets affect security?

Kuemerle: In an ideal world, you have security everywhere. For a chiplet architecture, you need a unique identifier for each chiplet and for the main die. Is there really a secure way to share keys between a chiplet and the main die, or multiple main dies? It adds a huge level of complexity, but you do have a couple options. One is you treat each piece of the system as a standalone entity. The other way is you rely on integration to make things secure. That’s an evolving space right now. We need a lot of focus and work to have something that’s as secure as possible if it’s built out of multiple pieces.

SE: What percentage of designs these days is being built using commercial chiplets.

Kuemerle: That’s tough to say, because right now we don’t have standards to put these LEGO blocks together cleanly if they come from disparate sources. It’s much easier for a company like Marvell to build our own chiplet platform and solution than to pull in chips from lots of places. The path of least resistance, if you have all the pieces you need, is to build these devices yourself — at least while we’re waiting for the industry to evolve.

Bishop: You’re on point there. It’s still a little bit early for that. The big players in the industry can afford to design them, and if you look at the chiplets that are out there, it’s all bespoke chiplets and even bespoke interfaces. It’s UCIe, but a little bit customized — or specialized BoW, or some version of that, but not the standard. At a lot of packaging conferences there will be a chiplet panel, and people will talk about when you will be able to put together chiplets like LEGOs to build a system just like a PCB. That won’t happen, though, until we have more suppliers for the integration technology and the cost is a lot lower than it is today. If you look at a high-end PCB, the analogy is always PCB components. There is a PCB in the cell phone in your pocket, and every component on there is custom. It’s too early to expect that you will see you LEGO-like chiplets that are not from the big players. It’s happening in pockets, and the industry starting to move there, but the cost and the availability are not there yet.

Mastroianni: You’ve got to start somewhere, but there’s a lot more work to be done.

Alam: For 15 years, people have been building their own chiplets for specific functions. And at a certain time, they come up with their own interface protocols for different options in other markets. So what would make you want to choose one of those open-market chiplets?

Kuemerle: That’s a functionality question. Does a chiplet I can find on the open market have all the functionality that I want? Does it have the link layer that will work for me? Is it going to be able to talk to other stuff that I’ve got going on? The dream is to be able to pull chiplets from multiple sources and get them to tie together well. But in a 2.5D configuration on an interposer, that stuff really needs to tie together because they’re right next to each other, and that form factor makes a big difference. If you know what all your different pieces are going to be, and you’ve got control over them, you can make sure they all fit together like LEGOs. But if you don’t, and everybody’s off building their own shapes, it’s a lot harder to make everything fit. Maybe advances in package technology could help us get a little more freedom and flexibility, which would be great. So maybe I can have something that’s a little further apart, or maybe it doesn’t have to be completely symmetrical. But right now we’re pushing the envelope with the amount of content we’re integrating. It’s a big risk to put together a lot of weird shapes.

SE: When something goes wrong with a chiplet, who’s responsible? And does that responsibility change throughout its lifecycle?

Mastroianni: You have to start with each of the chiplets and make sure they work, and then you need the ability to test them once they’re put into a package. So at least the diagnostics need to be there to make sure it’s really good. That’s possible today. But when you’re putting the system together, you also need to make sure it’s done properly. Ultimately the system integrator has the responsibility, as well as the burden to say that your routing technology has failed, for example.

Kuemerle: And that’s a big challenge.

Bishop: If you’re doing your chiplet integration at the same foundry that you’re building your chiplets, then there’s less directions to point fingers for blame. But when you’re integrating from multiple sources, the commercial side becomes more of a challenge.

Kuemerle: You can be doing massive integration, building a $1,000 module, but if there’s a sensitivity on a $10 chiplet, can you get that chiplet provider to pay you back for all the $1,000 modules that got wrecked as it was going through testing? That’s a really tough situation.

Mastroianni: It’s working for HBM. Now the question is whether you can really extend that model through standards and a standard way of testing.

Related Reading
Chiplets: 2023 (EBook)
What chiplets are, what they are being used for today, and what they will be used for in the future. Plus, the hurdles they face, the technologies involved, and how standards and ecosystems are forming in these early days of the technology.
The Race Toward Mixed-Foundry Chiplets
The challenges of assembling chiplets from different foundries are just beginning to emerge.

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