The Race Toward Mixed-Foundry Chiplets

The challenges of assembling chiplets from different foundries are just beginning to emerge.


Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear.

Many companies in the semiconductor ecosystem are still figuring out how they will fit into this heterogeneous chiplet world and what issues they will need to solve. While nearly everyone agrees chiplets are an essential building block for future designs, there are many hurdles to overcome.

“The big companies have been doing this type of technology in-house with their own custom solutions,” said Frank Ferro, senior director product management at Rambus. “Some of the advantages they realized early on are now getting other companies interested that don’t have the resources to do it themselves.”

One of the advantages of chiplets is the ability to fuse together technology developed using different manufacturing processes. “An I/O chip, for instance, could be built by one foundry, the core processor could be built by another foundry, then those could be put together in a chiplet,” Ferro said. “So in that sense, there’s potential for mixing and matching technology. You can say, ‘I get a great price from Foundry A, I have to deal with Foundry B, but now I can mix those together,’ because the chiplets can be thought of almost as standalone chips.”

Today, however, it’s not quite that straightforward. If multiple dies come from multiple places, the first step is to determine pin pitches for each.

“There is an option for standard packaging, which would have a flip chip 125 micron or 130 micron pin pitch versus something that would go on an interposer,” said John Park, product management group director for IC packaging and cross-platform solutions at Cadence. “That could be down to 35 micron pitch. That’s one of the challenges. If the pin pitch is down to 40 microns or 50 microns, I have to either use a silicon interposer or some sort of interconnect bridge to do that. That increases the cost, and is also why there is a standard package version, because if you put everything at a flip chip pitch of 125 micron or so, you can do that on a traditional laminate package, which is significantly less cost than going to silicon interposer or embedded bridge technologies.”

Once the interconnect is sorted out, and the packaging type has been decided, putting down the interconnect is not overly challenging, Park said, because it’s similar to a PCB and laminate-type package style of routing where 45º angles are needed. “In some cases, all angles are needed. Fillets are needed where the metal enters the pads. Differential pairs must be matched relative to one another in the [phase] control. Shielding is also needed. These are all things that the PCB tools have done, and instead of doing these giant pieces of metal, we’re going down to a micron or two. The PCB tools can scale that, so the biggest challenge for routing is just the amount of time it takes. In packaging, we’re used to dealing with a few thousand connections for signals even though there are a lot more than that for power and ground. There may be less than 50,000, but now with chiplets, you could be facing, 100,000+ connections, so an auto-router is needed to handle that kind of capacity.”

Mixed-foundry chiplet ecosystem
Mike Borza, Synopsys scientist, believes that in the long term, there will be a mixed-foundry chiplet ecosystem. “Until then, most of the integrated systems will be supplied by one vendor, and that vendor is the manufacturer of the chiplets as well as the integrator of the overall package.”

There may be some particular chiplets with small functions or even large functions that are coming from outside suppliers. “If there is competition amongst those outside chiplet suppliers, there needs to be standardization of the interfaces, or the integrator needs to be able to deal with disparate packages supplying the same interfaces. People do that, but it’s not convenient. It’s much more convenient to have standard pin-outs for standard functions, and you use the same node for every supplier,” Borza said.

This is why there is so much focus on the UCIe standard. “Regardless if you’re Foundry A or Foundry B, you have to adhere to the packaging technologies requirements,” said Mick Posner, product line senior group director for IP at Synopsys. “Let’s say you are doing an advanced interposer-based design. The interposer is the substrate that would connect the two die, and that usually defines a specific pin pitch. Both die would have to fundamentally adhere to this if they were going to be packaged across the substrate that happens to be on. That said, in theory, there is nothing stopping a customer from developing a die in TSMC and a die in another foundry, pulling in from another foundry and packaging all of those together. That’s one of the key benefits of a multi-die system. And while today most of this work is single vendor, in the near future that will change.”

Chiplet packaging technology requirements
An additional chiplet requirement comes from the package technology, Posner said. “There is an organic substrate, yes. At the other end is the interposer. Then there is a whole slew of new packaging technologies that sit in the middle, including InFO (TSMC’s Integrated Fan-Out), RDL (redistribution layers) fan-out, and others, all of which have their own path requirements.”

Multi-threaded routers are being developed to handle these bigger challenges, and Cadence’s Park noted the engineering teams doing these types of designs generally use a PCB-style router for the signal routing. “Then, in many cases, if the design has complex power structures, which are something you’d see in an IC tool, they’ll actually mix these together, taking the power and ground routing from an IC tool and merging that with signal routing. So it’s really the converging of the systems world and the IC — they are coming together, and that includes the tools and the expertise you need to do it. But in general, the layout is done by systems people that are used to doing that style routing. It’s just that there are a lot more connections now. This means there’s more of a bottleneck on the routing side.”

There are other benefits to chiplets, as well. “It takes the risk out of some of these chips if they’re so big and expensive,” said Simon Davidmann, CEO of Imperas Software. “Say the processor screws up. Take it off, put another one in. That’s a real benefit. If you’ve got an SoC, you can’t change the processor. If you’ve got a chiplet, you can build a new one with all the other blocks and it’s just like a printed circuit board. If you’ve got 1,000 components on a printed circuit board, one breaks, you unclip it, plug another one in, and it works. Even if it is in the field, and something fails, replacing one chip in a chiplet is still cheaper than throwing the board away, and redesigning a new board, if all I do is just redesign that little bit. Since chiplets are basically big blocks of hard IP so what happens is that if I’m building a chip, instead of getting Version 3 of a processor, getting a chip, then having to wait a year and do a new chip when Version 4 comes out, I can just change the chiplet, and when a new block comes out, I can use all the rest of the bits I’ve still got. I just change the chiplet processor from 3 to 4 and move forward.”

As far as the physical issues, Davidmann doesn’t see any real impact apart from a need to do more simulation and verification.

New chiplet challenges
Currently, large companies such as AMD and Intel use internally designed chiplets, basically decomposing an SoC or ASIC into different functions.

“To do that, since there is no ecosystem of chiplets, they need to be doing multiple chip designs concurrently because all these chips need to be designed to work together to build a whole system,” said Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software. “If it’s a large ASIC, you break it into hierarchical blocks. There’s reusable IP primarily for your analog and high-speed I/O. With chiplets, now you’re decomposing your ‘super ASIC’ into smaller chiplets, but you’re not necessarily stuck with having to use the same process and you can use that to your advantage. If you have a large processor, you can use a 5nm or 3nm process. If you have analog/mixed signal, you can use a cheaper process that works better in that. There may also be specialized IP that’s only available in a very expensive node. If you only need that for one interface, why not just build that into a chiplet?”

Fig. 1: IP in a chiplet ecosystem. Source: Siemens EDA

But it’s a very different story when it comes to chiplets developed by different foundries. “You have to worry about these standards and making sure you get all of the correct voltages,” Mastroianni said. “Even if it’s from the same foundry, you have to worry about this because they’re different lots, so by definition they’re two different chips. That means there are different corners, and you have to deal with that anyhow. If they were manufactured on different processes, that makes it a little more challenging. A lot of that is handled through the die-to-die interfaces — almost like a SerDes interface — which kind of decouples it, and those interfaces are designed to be to be like that. It’s more of an issue on those other signals, like the low-speed I/O that may need some connection, so you have to worry about it. But typically, those interfaces are not as critical. High-speed I/Os are covered through those standard protocols.”

While there is a lot of movement toward 3D design, it’s not clear that makes sense for commercial chiplets. “In 3D, the place-and-route tools will be able to support different technologies,” he said. “They are going to deal with that, and that’s a very IC, place-and-route-centric flow. Whether or not you even need models for each of those chiplets that are going to be put together, they’re really going to be designed together as a group. It is possible you may have a standard that you could sell as a chiplet, but that will be the exception.”

Today, most chiplet activity today is in 2.5D. “You may have multiple 3D chips on an interposer and other ASICs because again, even if you have 3D, there are practical limitations on how many you can stack due to thermal limitations,” Mastroianni said. “When you stack them up, you have to worry about heat. That’s one of the bigger challenges, along with being stuck with the reticle size. Yet you can get beyond that using interposers or organic substrates.”

How the chip/chiplet/system architects will work with the packaging technology teams and the ASIC design teams to determine what IP is available in different technologies is yet another significant aspect of chiplet design to overcome.

“There’s a lot more architectural planning that is needed compared to ASIC design, which is that once you have an ASIC and a spec, you just turn the crank and you do your chip. Chiplets are different. There are other steps involved there. Still, once you design that 3D chip, it still could be re-used as a chiplet. It will just be a three-high or a four-high chiplet, just like in HBM. There, you will need all the views of everything that will be integrated in a package,” he said.

Chiplet communication
How exactly one chiplet communicates with another is another challenge that needs to be sorted out, particularly with chiplets developed by multiple foundries. This is where much of the standards efforts have been focused.

“You simply can’t do anything with chiplets coming from somewhere else if you can’t communicate with it,” said Pim Tuyls, CEO of Intrinsic ID. “Then you need another chip in between that translates one type of communication to the other communication, and that only makes it more complex. It doesn’t become less complex with that. Connected with this is security. You cannot do security if the hooks and angles are not there. If the chiplet has no mechanism for public key crypto, for example, there is little you can do. Sometimes you can do a fix with software, but you have to be prepared for that. Standardization of the communication and security level for chiplets will become very, very important.”

Matthew Ozalas, master application development engineer and scientist at Keysight Technologies, said that ideally each chiplet is treated as a standalone block that’s insensitive to physical packaging. That’s not always an option, however.

“For example, chiplets in close proximity to one another might interact thermally, electromagnetically, or in other physical ways,” Ozalas explained. “To model such interactions, you would need to perform an analysis on the layout structures within the chiplets themselves. Foundries already are creating sophisticated models for packaging, but these packaging flows are currently based on the assumption that all the IP is contained within the foundry’s ‘umbrella.’ If there are chiplets from multiple foundries, higher-level assembly and analysis could become a major stumbling block. Sophisticated models of the circuit, the layout, and the substrate are all considered sensitive. So standardization would need to enable co-simulation of the lower-level structures within the chiplets while at the same time protecting each foundry’s individual IP through appropriate encryption. These IP and multi-physics issues are in addition to the more traditional layout-based assembly challenges like dissimilar stack-ups, connectivity, and verification across chiplets, which also must be dealt with in a standardized way.”

But how quickly a multi-foundry approach is developed remains to be seen. Geoff Tate, CEO of Flex Logix is confident in the ecosystem, but says initial implementations will largely be from the same foundry. “They’ll have different known-good-die approaches, mechanical specs will be different, and who wants to own figuring out what the problem is if there is one on a multi-chiplet device,” he said. “In all likelihood chiplets will only be used within one foundry’s ecosystem for now. TSMC may be willing to mix chiplets of their own design/process from multiple process nodes, because they understand the elements coming in and want the end customer’s business.”

Tate added that none of this will happen overnight. “There is not a standard set of chiplets available with standardized interfaces,” he said. There is not a standardized way of testing and guaranteeing the manufacturing reliability of chiplets (high-temperature and low-temperature tests have proven methodologies in chips, but that is in development for chiplets). There is not a proven, automated set of design tools for integrating chiplets onto substrates. There is not an ecosystem of suppliers that will integrate chiplets from multiple suppliers. One supplier doesn’t trust another supplier’s flows. The chiplets from different processes will have different thermal coefficients of expansion leading to mechanical reliability issues/concerns. If the assembled substrate doesn’t work, who owns the problem? And until a proven ecosystem develops and until the cost of substrates drops, chiplets won’t be practical for the main stream,” Tate added.

Chiplets are coming. The question is how quickly, how widely the chiplets will be sourced, and what are the ideal applications.

To be sure, all the kinks have not been worked out of the various processes in design and manufacturing to enable companies to pick from a menu of options, integrate these devices into a system, and be confident it will work as expected. That will take time. But the direction has been firmly established — and proven to work by some of the largest chipmakers — even if it’s not clear exactly when or how the rest of the semiconductor industry will get there, and what kinds of problems it will encounter along the way.

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Christopher Wendt says:

Re: “…in theory, there is nothing stopping a customer from developing a die in TSMC and a die in another foundry, pulling in from another foundry and packaging all of those together”. The one thing that will stop that practice is the concept of whom will the Navy sue when the submarine sinks because of multifoundry Chiplet failure?

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