Rapid Timing Constraints Signoff With Automated Constraint Management

Avoid surprises in layout-level or signoff static timing analysis.


Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a tool must be tied closely into the logic synthesis process to make it more likely that the generated gate-level netlist will meet the desired timing. Power, performance, and area (PPA) goals can only be achieved by running at the target clock speed, and this is compromised if there are any long paths in the design that violate setup times. Paths that violate hold times are even more troublesome since race conditions often require a chip turn to fix.

Signal path timing depends on both the delay of the gates and the transit time along the interconnects between the gates. In deep submicron chips, the interconnects usually dominate overall path delay. Thus, signoff-level STA cannot be performed until the design has been placed and routed, when the exact length of each path is known. It is essential for pre-layout estimates to be as accurate as possible, and for timing information to be passed intelligently and seamlessly between the different stages of the design process.

Timing constraints provide the mechanism to address this challenge by defining clock frequencies and waveforms, clock alignments, input and output timing requirements, multi-cycle path (MCP) and false path (FP) exceptions, and other critical information. Constraints are developed by the design team during the register transfer level (RTL) design phase. They are used in the frontend flow during logic synthesis as noted earlier, and in the backend flow to guide the place and route (P&R) layout process and to perform signoff STA.

Constraints may be modified, refined, or restructured from one stage to the next, and this is best done by automated translation rather than manual editing. Constraints may be “promoted” from IP blocks and lower levels of the design hierarchy to the SoC level or “demoted” in the opposite direction. As designs grow in size and complexity, it becomes harder to develop and these manage constraints and so automation is essential.

There are typically hundreds of timing constraints in multiple files, leading to complex interactions throughout the design flow. An incomplete set of constraints (under-constraining) can lead to critical design bugs since synthesis and layout tools can’t possibly optimize for unspecified requirements. Extra constraints (over-constraining) can lead to excessive runtimes as tools try to optimize for unreasonable or even conflicting constraints. SDC files must be accurate and consistent across the flow as they are passed between frontend and backend design stages.

The only way to resolve these issues is automated, comprehensive constraint management. The goal of this process is to avoid surprises in layout-level or signoff STA that require going back to make changes in the logic synthesis stage or to the design itself to meet PPA targets. This “shift left” from implementation/signoff to RTL level reduces design iterations and accelerates timing closure. There are several requirements that must be satisfied for effective timing constraint management:

  • The flow must start with an early, accurate, and complete set of constraints
  • Constraints must be translated automatically whenever possible
  • Constraints must be verified at multiple point in the flow
  • Constraints must be consistent across all levels of design hierarchy
  • Constraints must be consistent across all design stages
  • Equivalence checking must verify constraint consistency
  • MCP and FP exceptions must be verified

Synopsys Timing Constraints Manager (TCM) is a readily available solution that meets all these requirements and more. It supports the Synopsys Design Constraint (SDC) format, the industry standard for specification of timing constraints. TCM generates many timing constraints by analyzing the RTL design and performs precise, noise-free checks on constraints specified by the designers. It performs automatic translations between stages and runs equivalence checks to ensure that the SDC files are consistent.

From the RTL, constraints for clocks, clock groups, and timing exceptions can be automatically generated. Both the generated constraints and the designer-specified constraints are verified using a “lint” checker backed by formal verification that can detect many types of SDC errors. These include missing and incorrect clock definitions, missing input or output constraints, incorrect edge specifications, reconvergent paths, and conflicting constraints.

All MCP and FP timing exceptions are also verified. If any checks do not resolve during formal analysis, SystemVerilog Assertions (SVA) are generated and run with the RTL design in the Synopsys VCS simulator for dynamic verification. Alternatively, for unresolved checks, formal-fail SDC paths can be provided as an input to Synopsys VCS SDC, which enables native SDC-aware functional verification. For easy diagnosis and fixing of constraint errors and warnings, links are provided to the Synopsys Verdi Automated Debug System.

All translations of SDC files are performed automatically, with no need for designer intervention or manual editing. Constraint mapping, promotion, demotion, and merging are all automatic. For example, the SDC files for multiple IP blocks are combined and translated for use at the subsystem or full SoC level. Constraints for timing and other modes can be merged. RTL constraints are automatically mapped so that signal names match the post-layout netlist. Whenever a constraint file is translated, equivalence checking is performed on the original and generated files to ensure consistency.

This solution has been deployed on numerous real-world designs, with significant benefits to multiple project teams. Early in the flow, RTL designers get low noise SDC linting and MCP/FP exception verification, reducing their review effort by 90%. Subsequently, the implementation team leverages automatic promotion and demotion to ensure that the correct constraints are fed to the P&R stage. Overall, Synopsys TCM saves 6-8 weeks on a typical implementation schedule with automated constraints promotion methodology. Lastly, timing signoff is performed with 10X higher performance and a 5X reduction in memory usage on the netlist description of the design.

In summary, traditional ad hoc methods with manual translation of SDC files does not scale for contemporary SoC designs. Meeting PPA goals requires accurate timing constraints and automated management throughout the design flow for productive end-to-end timing signoff.  The Synopsys solution provides large gains in productivity and eliminates the possibility of a chip turn due to constraint errors. Watch this webinar for even more details.

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