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Closing The Post-Silicon Timing Analysis Gap


Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

A New Dimension Of Complexity For IC Design


Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is used to validate a design’s timing performance by checking all possible paths for timing violations. STA issues began popping up particularly with the introduction of hybrid bonding, a bumpless p... » read more

Improving Robustness And Minimizing Over-Pessimism In The Face of Rising Design Variability


Part 1 of this blog explored the problems facing designers working on Systems-on-a-Chip (SoCs) targeting energy-efficient design, and how Synopsys’ PrimeShield design robustness solution can help optimize designs for lower power while achieving aggressive time-to-market goals. This last part will delve into how the PrimeShield design robustness solution can help SoC designers optimize thei... » read more

Dealing With ECOs In Complex Designs


Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Using Static Analysis For Functional Safety


Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

Which Glitch Is Which?


Glitch is a commonly used term in modern vernacular, used to identify unexpected problems in everything from the space race, web site down time, or a crash of your latest mobile phone app. In electronics design glitch has a more specific meaning, referring to unnecessary signal transitions in a combinational circuit. Eliminating this extra switching activity can save power consumption, especial... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm


Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Low Power Meets Variability At 7/5nm


Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Next-Generation Liberty Verification And Debugging


Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Designers Face Growing Problems With On-Chip Power Distribution


The technology evolution in semiconductor manufacturing has led to chips with ever-higher power densities, which is leading to serious problems with on-chip power distribution. Specifically, the problems surrounding voltage drop—or IR drop (from V=IxR)—have become so acute that we have seen multiple companies starting to get back dead silicon from the fab. For example, a recent 7nm chip ... » read more

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