tag: static timing analysis

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

STA Strategies For Fast And Efficient Signoff Performance For Multi-Billion Instance Designs
By Manoz Palaparthi - 31 Jul, 2025 - Comments: 0

Contemporary AI, high-performance computing (HPC), mobile, and automotive designs continue to grow in size and complexity, putting a strain on the high-capacity compute required for static timing analysis (STA) workloads. Designs continue to grow at an unprecedented rate in size and complexity, outpacing the capacity of existing high-performance compute servers. A modern STA solution that can h... » read more

Static Timing Analysis: Cell Delay Vs. Cell Drive Strength
By Pamula Sai Srinivas - 13 Mar, 2025 - Comments: 0

Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI circuit operation is very similar. If the driving cell is strong, it takes less delay and changes the output quicker than a weaker driver, which produces a sluggish response and takes longer t... » read more

Rapid Timing Constraints Signoff With Automated Constraint Management
By Rimpy Chugh - 28 Mar, 2024 - Comments: 0

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a tool must be tied closely into the logic synthesis process to make it more likely that the generated gate-level netlist will meet the desired timing. Power, performance, and area (PPA) goals can o... » read more

Using Virtual Metal Fill To Predict The Impact Of High Level Nets
By Vamsi Thatha - 14 Sep, 2023 - Comments: 0

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

Using Virtual Metal Fill To Solve Real Design Problems
By Vamsi Thatha - 08 Jun, 2023 - Comments: 0

People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those e... » read more

True 3D Is Much Tougher Than 2.5D
By Brian Bailey - 23 Mar, 2023 - Comments: 0

Creating real 3D designs is proving to be much more complex and difficult than 2.5D, requiring significant innovation in both technology and tools. While there has been much discussion about 3D designs, there are multiple interpretations about what 3D entails. This is more than just semantics, however, because each packaging option requires different design approaches and technologies. And a... » read more

Tempus Timing Signoff Solution
By Cadence - 23 Nov, 2022 - Comments: 0

The Cadence Tempus Timing Signoff Solution is the fastest static timing analysis (STA) tool in the industry today with unique distributed processing and cloud capabilities enabling hundreds of CPUs to quickly complete even the largest designs. With full foundry certification and a comprehensive set of advanced capabilities, the Tempus solution delivers SPICE-accurate results to hundreds... » read more

Next-Generation Distributed Static Timing Analysis On The Cloud
By Ajit Sequeira - 26 May, 2022 - Comments: 0

Ever-growing chip size and complexity put pressure on every step and every electronic design automation (EDA) tool in the development flow. More decisions must be made at the architectural stage, stressing virtual prototypes and high-level models. Simulations become slower and consume more memory. Formal verification struggles to achieve full proofs. Logic synthesis and layout have a harder tim... » read more

Closing The Post-Silicon Timing Analysis Gap
By Ash Patel - 10 May, 2022 - Comments: 0

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

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