tag: static timing analysis

Using Static Analysis For Functional Safety
By Ed Sperling - 15 Jan, 2020 - Comments: 0

Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

Which Glitch Is Which?
By Pat Sheridan - 25 Jul, 2019 - Comments: 0

Glitch is a commonly used term in modern vernacular, used to identify unexpected problems in everything from the space race, web site down time, or a crash of your latest mobile phone app. In electronics design glitch has a more specific meaning, referring to unnecessary signal transitions in a combinational circuit. Eliminating this extra switching activity can save power consumption, especial... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm
By Ann Mutschler - 09 May, 2019 - Comments: 3

Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Low Power Meets Variability At 7/5nm
By Ann Mutschler - 11 Apr, 2019 - Comments: 0

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Next-Generation Liberty Verification And Debugging
By WeiLii Tan - 27 Sep, 2018 - Comments: 1

Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Designers Face Growing Problems With On-Chip Power Distribution
By Marc Swinnen - 13 Sep, 2018 - Comments: 0

The technology evolution in semiconductor manufacturing has led to chips with ever-higher power densities, which is leading to serious problems with on-chip power distribution. Specifically, the problems surrounding voltage drop—or IR drop (from V=IxR)—have become so acute that we have seen multiple companies starting to get back dead silicon from the fab. For example, a recent 7nm chip ... » read more

“Good Enough For Government Work?” Not Anymore.
By Ruben Molina - 26 Jul, 2018 - Comments: 0

When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as 40 years. To get an idea of how many people I’m talking about, there was a retirement party for at least 3 or 4 people every week just in our division. You can imagine tha... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Tech Talk: eFPGA Timing
By Ed Sperling - 03 May, 2018 - Comments: 0

Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

Pushing Performance Limits
By Brian Bailey - 08 Feb, 2018 - Comments: 0

Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

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