Pat Sheridan

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Pat Sheridan is responsible for Synopsys' signoff power analysis solutions marketing. He has 25+ years of experience in the marketing and business development of high-technology hardware and software products for Silicon Valley companies, joining Synopsys in 2010. Sheridan holds a BS degree in Computer Engineering from Iowa State University.

Author's Latest Posts

Which Glitch Is Which?

By Pat Sheridan - 25 Jul, 2019 - Comments: 0

Glitch is a commonly used term in modern vernacular, used to identify unexpected problems in everything from the space race, web site down time, or a crash of your latest mobile phone app. In electronics design glitch has a more specific meaning, referring to unnecessary signal transitions in a combinational circuit. Eliminating this extra switching activity can save power consumption, especial... » read more

Software Modeling And KPI

By Pat Sheridan - 23 Feb, 2017 - Comments: 0

In Software Modeling Goes Mainstream, Ed Sperling recently wrote how chipmakers are applying use case modeling techniques to better understand the interactions between software and hardware and how they impact system performance and energy efficiency. As the software content for multicore SoCs grows, these interactions are becoming increasingly complex. For system designers and SoC architect... » read more

Fast, Accurate, And Standards-Based

By Pat Sheridan - 01 Nov, 2016 - Comments: 0

Unlike the loosely timed models used for software development, which rely on a high level of abstraction to simulate as fast as possible, the communication between the architecture models in a virtual prototype for early performance analysis requires timing to be modeled more accurately. This tradeoff can seem like a big leap to some, spanning the gap from SystemC TLM-2.0 LT (loosely timed) ... » read more

Time For A DDR Background Check

By Pat Sheridan - 28 Jul, 2016 - Comments: 0

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

Talk Fast And Stop

By Pat Sheridan - 25 Feb, 2016 - Comments: 0

Power management. If you’re responsible for the design of low-power, energy-efficient electronic systems and SoCs, you need to have a power management strategy and you need to know as soon as possible if it will meet the demands of your product and its target applications. For example, dynamic voltage and frequency scaling (DVFS) is a power management strategy that adjusts the frequency an... » read more