Talk Fast And Stop

How virtual prototyping impacts power management.


Power management. If you’re responsible for the design of low-power, energy-efficient electronic systems and SoCs, you need to have a power management strategy and you need to know as soon as possible if it will meet the demands of your product and its target applications.

For example, dynamic voltage and frequency scaling (DVFS) is a power management strategy that adjusts the frequency and voltage operating points of the system based on the application activity. System performance and dynamic power dissipation are managed to achieve the best balance. Today’s blog title, on the other hand, is a pun based on Run Fast and Stop, a strategy used when it’s more energy efficient, due to leakage power considerations at 65nm and below, to complete the task at hand as soon as possible. (You may feel the same way about reading blogs).

Although the benefits of power management are more obvious for battery-driven mobile consumer products, any device should consume only as much power as absolutely required to perform a certain task. The increasing number of CPUs with their high frequencies, the increasing size of LCD screens, cameras and the multitude of radios and sensors, are driving the total power consumption beyond what is acceptable by the user. Only proper management of the power states within these devices will minimize total power consumption.

How is virtual prototyping helping? The release of the new IEEE 1801-2015 UPF 3.0 standard is a big step forward. With UPF 3.0, system-level power modeling and analysis using power-aware virtual prototypes is enabling architects and system designers to define systems that yield the greatest benefit in terms of energy efficiency, months earlier, before hardware is available. The figure below illustrates how component level power models are added to a virtual prototype in the industry’s first architecture analysis tool to support UPF 3.0:

Figure 1: Adding UPF 3.0 System Level IP Power Models to a Synopsys Virtual Prototype

Each system-level IP power model is an abstraction of the power behavior of a component, providing a specification of its power states and the associated power consumption data for each state. Models based on the new UPF 3.0 standard enable interoperability across virtual prototyping use cases and vendor environments. These abstracted power models enable early analysis of system-level power budgets and can be refined as more specific implementation information becomes available.

Figure 2: Example UPF 3.0 System Level IP Power Model

Software plays a significant role in device power management at runtime, as it controls and drives the hardware components which actually consume power. Once the power management policies are defined and optimized by the architect, virtual prototypes for software development can accelerate the development and debug of high quality power management software at multiple levels – across the drivers, operating system, and up through to the application layer. And just like other software development tasks using virtual prototypes, the software team can work in parallel to the hardware team, enabling software bring-up to support power management features as soon as possible.

So what’s the next step for your power management strategy? If you want to hear more industry “Talk” (“Fast” or otherwise) on how virtual prototypes and the new IEEE 1801-2015 UPF 3.0 standard are enabling system-level power analysis earlier in the development cycle, just “Stop by” DVCon on Wednesday March 02, 8:30 a.m. – 9:30 a.m. at the Doubletree Hotel in San Jose, for the Redefining ESL panel discussion moderated by Semiconductor Engineering’s Brian Bailey.

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