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tag: DVFS

How Climate Change Affects Data Centers
By Marie C. Baca - 25 Aug, 2022 - Comments: 0

Data centers are hot, and they may get even hotter. As climate change impacts temperatures around the world, designers are changing the computing hubs that are tied to nearly every aspect of modern life to make them more efficient, more customized, and potentially more disaggregated. These shifts are taking on new urgency as the tech industry grapples with months of sweltering temperatures o... » read more

Effectiveness of a Reinforcement-Learning Based Dynamic Power Manager In a SW Framework
By Technical Paper Link - 13 Jul, 2022 - Comments: 0

New technical paper titled "Low-Overhead Reinforcement Learning-Based Power Management Using 2QoSM" from researchers at ETH Zurich and Georgia Tech. Abstract "With the computational systems of even embedded devices becoming ever more powerful, there is a need for more effective and pro-active methods of dynamic power management. The work presented in this paper demonstrates the effectiven... » read more

Hertzbleed: A New Family of Side-Channel Attacks–Root Case: Dynamic Frequency Scaling
By Technical Paper Link - 01 Jul, 2022 - Comments: 0

  New research paper titled "Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86" from researchers at UT Austin, University of Illinois Urbana-Champaign (UIUC) and University of Washington can be found here. (preprint). This paper will be presented at the 31st USENIX Security Symposium (Boston, 10–12 August 2022). Summary explanation of the Hertzbleed ... » read more

Effect of Different Frequency Scaling Levels on Memory in Regard to Total Power Consumption in Mobile MPSoC
By Technical Paper Link - 06 Jun, 2022 - Comments: 0

New technical paper titled "CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems" from researchers at University of Essex, Nosh Technologies, and University of Southampton. Abstract "Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance r... » read more

Analytical Energy Model Parametrized by Workload, Clock Frequency and Number of Active Cores for Share-Memory High-Performance Computing Applications
By Technical Paper Link - 04 Apr, 2022 - Comments: 0

New academic paper from University of Mons (Belgium) and Universidade Federal do Rio Grande do Norte (Brazil). Abstract "Energy consumption is crucial in high-performance computing (HPC), especially to enable the next exascale generation. Hence, modern systems implement various hardware and software features for power management. Nonetheless, due to numerous different implementations, we ca... » read more

Clocks Getting Skewed Up
By Brian Bailey - 30 Mar, 2022 - Comments: 0

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

Tapping Into Non-Volatile Logic
By Bryon Moyer - 21 Apr, 2021 - Comments: 0

Research is underway to develop a new type of logic device, called non-volatile logic (NVL), based on ferroelectric FETs. FeFETs have been a topic of high interest at recent industry conferences, but the overwhelming focus has been using them in memory arrays. The memory bit cell, however, is simply a transistor that can store a state. That can be leveraged in other applications. “Non-v... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

Design For Reliability
By Brian Bailey - 15 Feb, 2021 - Comments: 1

Circuit aging is emerging as a mandatory design concern across a swath of end markets, particularly in markets where advanced-node chips are expected to last for more than a few years. Some chipmakers view this as a competitive opportunity, but others are unsure we fully understand how those devices will age. Aging is the latest in a long list of issues being pushed further left in the desig... » read more

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