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Leverage Functional Interfaces For High-Speed Test Access During All Phases Of The Silicon Lifecycle


Chip testing used to be straightforward. The development team used fault simulation to select a subset of the functional tests that could detect most possible manufacturing faults. These were translated to test patterns that ran on automated test equipment (ATE) to screen out defective dies at wafer test and bad packaged chips in final test. Lots of new technology was introduced over time, incl... » read more

Closing The Post-Silicon Timing Analysis Gap


Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

If These Chips Could Talk: Actionable Insights From Path Margin Monitors


One of the most important current trends in electronics is the gathering and analysis of big data to reap benefits in cost, power, performance, and reliability. This is becoming common in the chip development flow. For example, data harvested from simulation regressions can aid in debug and reaching coverage goals. Machine learning (ML) uses the results of many passes through implementation (lo... » read more

New Parasitic Extraction Requirements In Custom Design For The Next Wave Of SoCs


Fast growing markets like 5G, biotechnology, AI, and automotive are driving the new wave in semiconductor design and the need for highly integrated system on chip (SoCs). Power management, sensors, RF and precision analog functionality are all integrated on the same substrate which poses new challenges for custom design tools. Specifically, there are new challenges for parasitic extraction that... » read more