Shreedhar Ramachandra is a R&D Engineer, Senior Staff, in the low power verification team in the verification group at Synopsys. He has 14+ years of experience, starting his career as an ASIC design and verification engineer before moving to EDA (Electronic Design Automation), focused on architecting low power simulation products starting from Archpro MVSIM. He currently works as an Application Engineer for Synopsys’ VCS NLP product and also represents Synopsys in the IEEE-1801 UPF Committee.