中文 English

Power-Aware Test: Addressing Power Challenges In DFT And Test


Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

Primary, Anonymous, or What?


Top level primary I/Os remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications are multifold for RTL and gate level simulations of them. This paper studies the “simulation-impacting” features of design top IOs and the effect of each feature on v... » read more

The Many Flavors Of UPF: Which Is Right For Your Design?


Energy efficient electronic systems require sophisticated power management architectures that present difficult low-power verification challenges. Accellera introduced the Unified Power Format (UPF) standard in 2007 to help engineers deal with these complex issues. To keep pace with the growing complexity of low-power designs, the UPF standard has itself continued to evolve through the relea... » read more

Customizing Low-Power Platforms Using UPF Dynamic Properties


Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

Probing UPF Dynamic Objects


This paper presents a new low-power verification methodology that makes it possible to continuously monitor the dynamic properties of UPF objects and utilize the information to develop custom low-power verification environments. Based on UPF information model concepts, it allows querying of any dynamic properties of UPF objects through a Tcl API and passing object information on to appropriatel... » read more

Open-Source Verification


Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

Power Management And Integration Of IPs In SoCs: Part 2


Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, And Now UPF 3.1


UPF is the fastest evolving IEEE standard, and UPF 3.1 is a major milestone in its evolution. This paper provides an in-depth analysis and relevant examples of all the new features introduced in UPF 3.1 along with semantic differences with earlier versions. It also highlights migration challenges to help users migrate from existing power formats to UPF 3.1. To read more, click here. » read more

Power Management And Integration Of IPs In SoCs: Part 1


IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

← Older posts