Power Complexity On The Rise


New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Rapid Evolution For Verification Plans


Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Extending Portable Stimulus


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Shift Left Power-Aware Static Verification


Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification


By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Four Steps For Static Verification Of Low Power Designs Using UPF With VC LP


Low power consumption has always been a key requirement for portable electrical and electronic devices. In recent years, this requirement has been extended to many more categories of end products. The electronics industry has developed a wide range of techniques for power management and has defined the Unified Power Format (UPF) to describe design intent for some of the most common methods. Suc... » read more

Empowering UPF Commands With Effective Elements Lists


The Unified Power Format (UPF) is intended for power management, power aware verification, and low power implementation. The more we explore the inherent features of UPF commands and options, and comprehend their interrelation, the more we become accurate, productive, and consistent in developing UPF for our intended purposes. Although the UPF is very well defined through the IEEE 1801 LRM, ... » read more

Effective Elements List And Transitive Natures Of UPF Commands


Although UPF is very well defined through IEEE 1801 LRM, it is often difficult to comprehend many primitive and inherent features of individual UPF commands-options or relations between different varieties of UPF commands-options. In this paper, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inheren... » read more

Shift-Left Low Power Verification With UPF Information Model


By Himanshu Bhatt, Shreedhar Ramachandra and Narayanan Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power testbenches that can monitor the UPF objects and react to the state changes of UPF objects. To meet this requirement for the user to... » read more

Using Less Power At The Same Node


Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

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