EDA On Board With New Package Options


A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

Power Management And Integration Of IPs In SoCs: Part 2


Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

Shift Left Power-Aware Static Verification


Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification


By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Empowering UPF Commands With Effective Elements Lists


The Unified Power Format (UPF) is intended for power management, power aware verification, and low power implementation. The more we explore the inherent features of UPF commands and options, and comprehend their interrelation, the more we become accurate, productive, and consistent in developing UPF for our intended purposes. Although the UPF is very well defined through the IEEE 1801 LRM, ... » read more

Shift-Left Low Power Verification With UPF Information Model


By Himanshu Bhatt, Shreedhar Ramachandra and Narayanan Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power testbenches that can monitor the UPF objects and react to the state changes of UPF objects. To meet this requirement for the user to... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation


By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric


Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

Power-Aware Static Checks: Static Checker Results And Debugging Techniques


In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

Three Steps To Low Power Coverage Closure


By Awashesh Kumar and Madhur Bhargava Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these elements at a high abstraction level. However, power-aware coverage closure is difficult to attain and complex by nature. Existing low-power coverage methodo... » read more

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