EDA On Board With New Package Options

But with so many variations in multi-chip packages, there isn’t a single design flow.


A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions.

Challenges range from how to architect a design, how to explore the best options and configurations, how to phase the actual design process, and which tools to use for planning, design, implementation and validation. Flows are well established for the individual chips that are used in a package, putting the pieces together is much more problematic. The general consensus is that while many point tools exist, there isn’t just one flow, or even a complete flow, from a single vendor. That’s both good and bad.

“This is not your father’s IC packaging,” said John Park, product management director for IC packaging and cross-platform solutions at Cadence. “No one company has the perfect flows for the latest variations of packaging.”

Increasingly, as more information is being brought from the board level to the silicon level, thanks to semiconductor dimensions allowing for higher levels of integration, it effectively brings functionality of the surrounding devices into one package.

“With this higher level of integration, we are trying to achieve lower latency, smaller form factor, and lower power,” said Rita Horner, senior staff, product marketing manager at Synopsys. “All of that is creating a different level of complexity along with new challenges. There are so many different point tools in the market that it’s alphabet soup, and people are very confused. The key is how to you make the implementation happen.”

Fig. 1: Timeline of different packaging technologies. Source: Cadence

It wasn’t long ago that nobody on the design side of the industry wanted to talk about packaging, and it was treated as a necessary evil to spread out the I/O in a chip to protect it from the elements.

“It was easier to test a package than it was something at the wafer level, and it was all about avoiding negative impact on the performance of the chip, both electrically and thermally. That’s the old way of thinking,” Park said. “The modern day vision of packaging is that it’s the hottest thing going, and the reason for this is that people now look to packaging, as part of the ‘More Than Moore’ trend, to be able to add their uniqueness, their value, their extra special ingredients to their end products through these advanced packaging technologies. A lot of this is brought on because of through-silicon vias and advancements in high-density RDL [fan out wafer-level packaging], and 3D, among other approaches. Also, depending on the device that’s going to be built, whether it is a hearing aid or a smart watch or something else that’s typically pretty small, the actual mechanical form factor of the end product dictates how things will be packaged.”

Today, the two main 2.5D silicon interposer-based approaches are re-partitioned FPGA or processor, with HBM next to a processor. “There, it starts to become more like a chip and less like a BGA or PCB,” he said. “Over time, we moved from mechanical to PCB, and now we’re moving to more IC-like approaches from a tool perspective. Now the considerations include routing silicon that’s not really true silicon. On most designs, it’s a passive interposer, meaning just metallization, so you can do it with old fashioned PCB BGA tools because they’re used to working with adding length based on meandering traces, rather than inserting buffers, as an example. Those flows today are the most complex. It doesn’t mean they aren’t getting done. Everyone’s taping these things out, but they are the most complex and they work across multiple tools. For designs being taped out today, the chips are designed independently of one another. They close on timing. They tape them out. Then then they do a verification step so that the pads align, and then they stack them in three dimensions. There is no, ‘stick a bunch of wafers together and concurrently floorplan across them, use route resources across the multiple chips in the stack, close timing across multiple chips in the stack.’ That’s the area that requires you to use an IC design tool, not one of these old-fashioned tools. This is that hard break. Just like when the industry went from leadframe to BGA. It’s happening with the next generation of 3D-IC.”

Horner observed that the ideal situation is to have a common unified platform where all the information is brought into the simulation environment. Then enough information needs to be brought in to extract the parasitics and use simulation to make sure the wiring, the spacing, and the width of traces for the interconnect or the shielding are all going to meet the performance requirements. “In past, when you did the multi-die in the package, you had very few traces going between every part,” she said. “Now, with HBM you have thousands for one HBM connection. It’s very complex, and that’s why we are seeing silicon interposers enabling the interconnect, because it allows the fine granularity of the width and spaces that are needed for this level of density.”

Some of the requirements for advanced packaging today include being able to understand the many ways chips can be attached to package designs, whether it’s wire bond, flip chip, whether it is stacked, or whether it’s embedded. “There are lots of different ways of patching these diodes and packages. You have to have a tool that understands the intricacies of that kind of cross section of the design,” Park noted.

One consideration that frequently gets overlooked is the connectivity use model. “This is important because the chip designer may take the RTL and netlist it to Verilog, and that’s the connectivity. The board people use schematics for their connectivity. Then, the packaging people sit somewhere in the middle, and for a lot of the conductivity, they have the flexibility to assign the I/Os based on better routing on the board level. There, they need the ability to drive the design with partial schematic, and then the flexibility to then create their own on-the-fly connectivity to the I/O that are somewhat flexible, and the ability to work in spreadsheets. It’s not a single source for the connectivity, but it’s more important to have a really flexible connectivity use model that allows you to drive the schematics, spreadsheets, build connectivity on the fly, etc.,” he said.

Fig. 2: A small sample of different packaging options. Source: Cadence

Verifying packages
Even for tool providers that skirt these packaging issues right now, the time is coming when verification will take packaging into account.

“The packaging aspect comes into play when physical design verification takes place,” said Shubhodeep Roy Choudhury, CEO of Valtrix Systems. “Our input usually goes in during the functional verification, where we need to determine that all of the bugs are found and the coverage is complete. Then, the implementation goes into the hands of the implementation team.”

This can vary greatly, because packaging is chosen by the requirements of the final chip.

“What temperatures, voltages, conductivity, how many pins you need, etc. — those are all electrical requirements set in front of you,” said Aleksandar Mijatovic, design engineer at Vtool. “You’re actually choosing the packaging appropriate to your design. It’s a completely new science, and a very serious one. Breakthroughs are expected to be made here. We are near the end of nanometric revolution, so everything we have in a process now is being improved to its maximum in order to get newer and better chips.”

That doesn’t necessarily mean things will change quickly, however. “Even when there is a breakthrough with either organic semiconductors or germanium semiconductors, it will take a lot of time to set up the technology and process to the quality of those we have now in silicon,” Mijatovic said. “It took almost half a century to be here, so I do not expect that something can change silicon in the following 10 or 20 years for a commercial market.”

EDA challenges
For the most part, tools exist to develop advanced packages today. “Most everything that people want to do can be done with EDA tools,” said John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business. “We’re getting to a point where some of those flows are more clearly and cleanly defined. This means if you’re new to it, you can pick it up without too much difficulty and make the transition.”

Still, challenges exist for users in working through the different ways that each vendor approaches advanced packaging, Ferguson said. “We know how to do it, but we know more than one way to do it. Which is the best way? What’s going to get me through the fastest and the cleanest? These questions may be a bit of a hurdle. At the end of the day, somebody has to make those decisions. When it’s the foundry, at least you’ve got somebody who’s made that decision up front, if they’ve documented one and not the other, or they bless one and not the other. This can be a good thing, but it also limits you in exploring alternatives.”

On the advanced packaging design horizon, there is still plenty of work to be done including addressing stress and thermal impacts — not high-level thermal considerations, but how thermal impacts transistors in the dies and whether that will have a major impact on how the whole system behaves, Ferguson noted.

There is a growing need for very fast, almost real-time, thermal analysis in design today. “If there are three dies stacked, for the center die — which is sandwiched between the top die and the bottom die — the thermal dissipation channel will be limited,” said Norman Chang, chief technologist for the semiconductor business unit of Ansys. “Customers have been saying that when they are designing a 3D-IC and trying out different power in the blocks partition — in the top die, bottom die, and in the center die — they need to determine how much power they can put on these three different dies. They also need to determine the number of thermal vias needed for thermal dissipation. If you have a lot of power in the center die, and you are going through the bottom die to the package and PC board, then you need to have more thermal vias from the top die to the center die because there’s no thermal dissipation channel. Everything has to go through the center die.”

All of these tradeoff decisions need to be made early in the design process, given the many configurations for power, partitions of the power, different blocks, and different placement of the blocks in the chip. To do this, Ansys is looking to machine learning-based methods to perform on-chip thermal analysis, which can be done within seconds or no more than a couple minutes for every possible workload.

Foundry challenges
Mentor’s Ferguson sees the industry as just on the cusp of the foundries determining how to roll this out in a mass production fashion. “Today, there’s still a lot of hand-holding,” he said. “The foundries start by delivering reference flows to give an example of how to step through the different tools and the flows.”

EDA tool providers then work with the foundries on those reference flows. And because of the unique requirements of each company, decks are typically created for each customer. As these technologies and flows evolve and mature, so too will the foundry flows to become more streamlined.

This will take time, however. Synopsys’ Horner said that while the foundry flows for advanced packaging exist, it’s piecemeal with a lot of standalone disconnected tools.

“What the market needs to address to make this actually successful is that the current point tools are running out of bandwidth,” she said. “Those tools were designed for only one technology node at a time. They’re not able to integrate multiple technologies at the same time. They don’t have the capacity to have the large number of databases that need to be combined. Yes, the flows are there. The fabs already have created some of these flows and have ironed them out. But they consist of a slew of lots of tools — alphabet soup again. And a lot of them have different data formats going from one platform to another platform. In order to actually get the product designed and verified, you have to do so many iterations, on and on, and the long loop back and cycles, before you can actually get something reasonable — and a lot of things are afterthoughts.”

Many aspects of advanced packaging design need to be modeled and considered. “You need a model tool for thermal, you need a model tool for signal integrity. But then it’s very complex — you cannot afford going from one tool to another tool. You need to be able to have a cohesive thermal-aware environment, signal integrity-aware environment to make this thing work as you’re moving your devices around, to know where the heat is going to be a problem. That’s the platform that is required to make these multi-chip devices successful and to get to production level quickly. Otherwise, it’s going to take years and years. You miss the boat in the next release just because you’re trying to figure out how to get rid of the heat and still be able to compact everything in the same package,” Horner said.

At the same time, the industry to some extent is moving to the point now of adding some consistency and predictability that, if a chip is developed according to certain rules that are within the tools, that it will probably yield pretty well and behave properly and as expected out in the market.

“Every one of these designs is custom,” she said. “They’re unique, and you’re adding more complexity to them, so every design is going to be unique. And they each have their own challenges, whether you put the memory in the middle of the sandwich or you put it on top. If you’re going to put the CPU and the GPU on the bottom or the top, then you have to have through-silicon vias to connect to the bottom into the substrate. How do you distribute the heat? Where do you put the device on? Every design is going to be unique, and it is going to have its own challenges. But the techniques are being understood. The challenges are being recognized, and the tools are getting in place so the features and functions are getting placed.”

Nevertheless, advanced packaging is real, and for many designs at leading-edge nodes it is essential. Just shrinking features no longer provides the performance and power benefits required to justify the cost of the design.

“We have the knowledge for how to pull this solution together,” said Horner. “We have the capability to integrate all these different functions in the same database, and bring them together so they can run more efficiently to generate more of a DRC-aware environment that you can run auto routing without making a lot of mistakes. You can get the ultimate densities. You can do auto shielding when you need to. You can have a DRC-aware, power-aware, signal integrity-aware or thermal-aware design without having to go from one tool to another tool.”

But as with anything related to complex chip design, making all of those pieces work together seamlessly will take time.

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Shen says:

Not once does the author define what the acronym “EDA” means. Nice read, but continuously wondering what EDA means.

Linda Christensen says:

Hi Shen,
It stands for Electronic Design Automation.

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