Blog Review: Mar. 14

Cadence's Meera Collier considers the issues of bias implementation in algorithms and AI systems, and whether immense training sets can really solve the problem. Mentor's Cristian Filip digs into the evolution of signal integrity analysis methods and why different data rates require different solutions. Synopsys' Naveen G explains key features introduced in the latest generation of interc... » read more

GDDR6 PHYs: From The Data Center To Self-Driving Cars

The demand for ever-increasing bandwidth has resulted in a growing interest in GDDR across a number of market verticals, including data centers and the automotive sector. As an example of the former, deep learning applications require ever-increasing speed and bandwidth memory solutions in the data center. In deep learning and other emerging technologies, GDDR memory can help companies addre... » read more

The Promises And Challenges Of 7nm

Despite a waning Moore’s Law and the increasing costs of advanced process nodes, the semiconductor industry is steadily approaching 7 nanometers (nm). The demand for 7nm is driving expected initial tape-outs from fabs by the end of 2017, with initial volumes beginning in 2018 and ramping up by 2019. Silicon fabbed on 7nm nodes will offer a number of benefits for chipmakers, including lower po... » read more

Blog Review: Oct. 18

Mentor's Nitin Bhagwath suggests some ways to deal with undesirable signal integrity effects in DDR designs. Cadence's Ken Willis argues that for multi-gigabit serial link interfaces, signal integrity analysis should start upstream of the traditional post-layout verification step. Synopsys' Ravindra Aneja contends that understanding formal core data can reduce the overall effort and short... » read more

Understanding SerDes Signal Integrity Challenges

Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

Turning Signal Integrity Simulation Inside Out

So what does it mean to turn signal integrity simulation inside out? Modern simulation has physics-based solvers in the foreground supported by circuit and system simulation rather than the other way around. All electronic design is fundamentally based on Maxwell’s equations, so naturally the most rigorous way to deliver accurate simulation of high-performance systems is to solve those equ... » read more

The Week In Review: Design

Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

7nm Design Success Necessitates A Multi-Physics Approach

Whether you are designing an energy efficient mobile device, or an ADAS platform with stringent reliability requirements, or a high performance enterprise networking system, chips fabricated on advanced technologies such as 7-nanometer (nm) process and 2.5/3D or wafer level packaging can provide several advantages. Designs using these technologies consume less power while delivering higher thro... » read more

Calibre xACT Parasitic Extraction Supports Signal Integrity At Advanced Nodes

At advanced nodes, signal integrity analysis requires precise characterization, which in turn requires an accurate extracted netlist. Models that handle new impacts on parasitic extraction at advanced nodes, including multi-patterning, finFETs, and resistance and capacitance effects, must be used. Learn how the Calibre xACT extraction tool supports these advanced foundry device models and leadi... » read more

System-Aware Full-Chip Power Integrity And Reliability

At the core of every electronics system is a chip that has to meet multiple conflicting requirements such as increased functionality, best power efficiency, highest reliability, lowest design cost and short design schedule. Meeting these requirements poses a major challenge, especially for systems on chip (SoCs) that are designed using advanced processes. Ensuring that the SoCs meet power an... » read more

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