tag: signal integrity

From Known Good Die To Known Good System With UCIe IP
By Manuel Mota - 11 May, 2023 - Comments: 0

Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

Ensuring Signal And Power Integrity In Today’s High-Speed Designs
By Pavani Jella - 08 Dec, 2022 - Comments: 0

Leading-edge chip desiLeading-edge chip design was never easy, but it’s getting harder all the time. Rapid advances in communication systems are driving data rates higher. With the emergence of artificial intelligence (AI) applications and the increased need for data processing, high quality data transfer is increasingly critical. Faster data rates and more complex protocols are exacerbating ... » read more

What’s So Different About Interposer Signal Integrity?
By Kelly Damalou - 28 Oct, 2022 - Comments: 0

By Kelly Damalou and Pete Gasperini To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an impressive evolution over the last several decades. Their development encourages technological advancement in applications like high-performance computing, Artificial... » read more

Reducing Schedule Slips With Automated Post-Route Verification Of SerDes High Speed Serial Links
By Todd Westerhoff - 01 Sep, 2022 - Comments: 1

Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection, and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype d... » read more

DDR5: How Faster Memory Speeds Shape The Future
By Ben Miller - 27 Jun, 2022 - Comments: 0

Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the data in memory. DDR is used everywhere — not just in servers, workstations, and desktops, but it is also embedded in consumer electronics, automobiles, and other system designs. DDR SRAM is used for running applications and d... » read more

IC Reliability Burden Shifts Left
By Ann Mutschler - 23 Jun, 2022 - Comments: 0

Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

Meeting 112 SerDes Based System Design Challenges
By Madhumita Sanyal - 12 May, 2022 - Comments: 0

The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25Tb/s (terabytes) to 51Tb/s and soon to 100Tb/s. The industry has chosen Ethernet to drive the switch market, using 112G SerDes or PHY technology today and 224G SerDes in the future. This article describes how designers can overcom... » read more

Using In-Design Analysis Flows To Resolve Signal Integrity Issues
By Avijeet Singh - 06 May, 2021 - Comments: 0

In today’s ever-shrinking IC package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to find out the layout mistakes by looking at the changing impedance values and high coupling due to nearby signals. Unfortunately, layout engineers... » read more

Integrity Problems For Edge Devices
By Brian Bailey - 14 Sep, 2020 - Comments: 0

Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

EDA On Board With New Package Options
By Ann Mutschler - 22 Jul, 2020 - Comments: 2

A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

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