Pushing Memory Harder


In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Multiphysics Simulations for AI Silicon to System Success


Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed de... » read more

GDDR Accelerates Artificial Intelligence And Machine Learning


The origins of modern graphics double data rate (GDDR) memory can be traced back to GDDR3 SDRAM. Designed by ATI Technologies, GDDR3 made its first appearance in NVidia’s GeForce FX 5700 Ultra card which debuted in 2004. Offering reduced latency and high bandwidth for GPUs, GDDR3 was followed by GDDR4, GDDR5, GDDR5X and the latest generation of GDDR memory, GDDR6. GDDR6 SGRAM supports a ma... » read more

Blog Review: June 19


Mentor's Rebecca Lord digs into signal integrity complications and why today's high frequency signals make it important to understand the physics of transmission lines. Cadence's Meera Collier points to the need to recognize diversity and nuance when compiling AI training datasets and avoid the oversimplification that can lead to bias. Synopsys' Deepak Nagaria checks out the new features ... » read more

Delivering High-Speed Communications: The Back Story


Back in January, I posted a blog about what it takes to deliver high-speed communication. In that post, I talked about a new test board for our high-speed 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes. We collaborated with several companies to build a high-precision board that could be used to test our SerDes in a system context. At that time, we were just finishing the opening act for thi... » read more

Engineering The Signal For GDDR6


DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

Latency Under Load: HBM2 vs. GDDR6


Steven Woo, Rambus fellow and distinguished inventor, explains why data traffic and bandwidth are critical to choosing the type of DRAM, options for improving traffic flow in different memory types, and how this works with multiple memory types.   Related Video GDDR6 - HBM2 Tradeoffs Why designers choose one memory type over another. Applications for each were clearly delineate... » read more

GDDR6 And HBM2: Signal Integrity Challenges For AI


In a nutshell, Artificial Intelligence (AI) and its growing list of applications demand a considerably large amount of bandwidth to push bits in and out of memory at the highest speeds possible. AI has been getting a lot of industry attention, and certainly it’s not a new phenomenon because it’s been gaining even greater traction in the last year or two. This is especially true since a n... » read more

GDDR6: Signal Integrity Challenges For Automotive Systems


Signal integrity (SI) is at the forefront of SoC and system designers’ thinking as they plan for upcoming high-speed GDDR6 DRAM and PHY implementations for automotive and advanced driver assistance system (ADAS) applications. Rambus and its partners are closely looking at how GDDR6’s 16 gigabit per second speed at each pin affects signal integrity given the cost and system constraints for a... » read more

2.5D, 3D Power Integrity


Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

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