中文 English

DDR5: How Faster Memory Speeds Shape The Future


Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the data in memory. DDR is used everywhere — not just in servers, workstations, and desktops, but it is also embedded in consumer electronics, automobiles, and other system designs. DDR SRAM is used for running applications and d... » read more

IC Reliability Burden Shifts Left


Chip reliability is coming under much tighter scrutiny as IC-driven systems take on increasingly critical and complex roles. So whether it's a stray alpha particle that flips a memory bit, or some long-dormant software bugs or latent hardware defects that suddenly cause problems, it's now up to the chip industry to prevent these problems in the first place, and solve them when they do arise. ... » read more

Meeting 112 SerDes Based System Design Challenges


The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25Tb/s (terabytes) to 51Tb/s and soon to 100Tb/s. The industry has chosen Ethernet to drive the switch market, using 112G SerDes or PHY technology today and 224G SerDes in the future. This article describes how designers can overcom... » read more

Using In-Design Analysis Flows To Resolve Signal Integrity Issues


In today’s ever-shrinking IC package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to find out the layout mistakes by looking at the changing impedance values and high coupling due to nearby signals. Unfortunately, layout engineers... » read more

Integrity Problems For Edge Devices


Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

EDA On Board With New Package Options


A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

Power Impact At The Physical Layer Causes Downstream Effects


Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Signal Integrity Through The Years


Yesterday, I started to talk about how new technologies find their way over time into EDA tools in my post How Technologies Get into EDA. Let's look at signal integrity as an example. We used not to worry about signal integrity at all. The first time anything like that impinged on my consciousness was in the early 1980s when we realized that we needed to start to consider the inductance... » read more

Thermal Challenges In Advanced Packaging


CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

GDDR6 Drilldown: Applications, Tradeoffs And Specs


Frank Ferro, senior director of product marketing for IP cores at Rambus, drills down on tradeoffs in choosing different DRAM versions, where GDDR6 fits into designs versus other types of DRAM, and how different memories are used in different vertical markets. » read more

← Older posts