The Next Advanced Packages


Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

SEMI 3D1 – Terminology For Through Silicon via Geometrical Metrology


Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). Click here to read more, fee for access. » read more

Making Silicon Photonics Chips More Reliable


Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn't so simple. While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That's mostly due to the fact that Moore's Law scaling h... » read more

Scaling CMOS Image Sensors


After a period of record growth, the CMOS image sensor market is beginning to face some new and unforeseen challenges. CMOS image sensors provide the camera functions in smartphones and other products, but now they are facing scaling and related manufacturing issues in the fab. And like all chip products, image sensors are seeing slower growth amid the coronavirus outbreak. Manufactured a... » read more

Effective Post-TSV-DRIE Wet Clean Process For Through Silicon Via Applications


Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen... » read more

Finding Defects In IC Packages


Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Pushing Memory Harder


In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

The Next New Memories


Several next-generation memory types are ramping up after years of R&D, but there are still more new memories in the research pipeline. Today, several next-generation memories, such as MRAM, phase-change memory (PCM) and ReRAM, are shipping to one degree or another. Some of the next new memories are extensions of these technologies. Others are based on entirely new technologies or involve ar... » read more

HBM2E: The E Stands for Evolutionary


Samsung introduced the first memory products in March that conform to JEDEC’s HBM2E specification, but so far nothing has come to market—a reflection of just how difficult it is to manufacture this memory in volume. Samsung’s new HBM2E (sold under the Flashbolt brand name, versus the older Aquabolt and Flarebolt brands), offers 33% better performance over HBM2 thanks to doubling the de... » read more

← Older posts