Defect Challenges Grow For IC Packaging


Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages. While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools. For years, p... » read more

Redefining The Power Delivery Network


Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

EDA On Board With New Package Options


A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

The Next Advanced Packages


Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

SEMI 3D1 – Terminology For Through Silicon via Geometrical Metrology


Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). Click here to read more, fee for access. » read more

Making Silicon Photonics Chips More Reliable


Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn't so simple. While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That's mostly due to the fact that Moore's Law scaling h... » read more

Scaling CMOS Image Sensors


After a period of record growth, the CMOS image sensor market is beginning to face some new and unforeseen challenges. CMOS image sensors provide the camera functions in smartphones and other products, but now they are facing scaling and related manufacturing issues in the fab. And like all chip products, image sensors are seeing slower growth amid the coronavirus outbreak. Manufactured a... » read more

Effective Post-TSV-DRIE Wet Clean Process For Through Silicon Via Applications


Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen... » read more

Finding Defects In IC Packages


Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

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