Innovative Scalable Design-Based Care Area Methodology For Defect Monitoring In Production

How to improve time to results, increase efficiency, and add consistent sensitivity for cross-product defectivity analysis.


By Ian Tolle, GlobalFoundries, and Ankit Jain, KLA-Tencor

The use of design-based care areas on inspection tools [1, 2] to characterize defects has been well established in recent years. However, the implementation has generally been limited to specific engineering use cases, due to the complexity involved with care area creation and inspection recipe setup. Furthermore, creating, organizing, optimizing and auditing all these care areas per inspection step and per device can be time- consuming. In this work we demonstrate a novel methodology for the implementation of NanoPointTM care areas across all inspection steps in semiconductor process flow, using a technology-specific set of care area generation rules, rather than rules targeted to particular defect of interest (DOI). This approach enables optimal recipe sensitivity across the entirety of a chip, by segmenting care area coverage into high-sensitivity, intermediate- sensitivity and low-sensitivity regions based on pattern density. Furthermore, this methodology is scalable in nature which means that the care area generation rules are defined only once per technology node, and thus, can enable automated care area generation for any chip design within a technology node, with no user input required. Inspection recipes created with this type of care area demonstrate consistent sensitivity for cross-product defectivity analysis in a high volume manufacturing (HVM) wafer fab.

As design rules shrink, transistor density increases due to smaller patterns printed on the wafers. Smaller than 28nm technology nodes enable printing small features by leveraging advanced multiple patterning techniques like series of litho – etch (LE)n, self-aligned double patterning (SADP) and other variants of the two. As the patterns get smaller, smaller defects classified as non-killers cause yield and reliability challenges. Also, printing smaller patterns rerquires multiple hard-masks, leading to more film depositions, more materials to be cleaned and higher variability in the process. Further, for performance improvements, different materials are used commonly for stress/strain on the channel and also exotic materials for metal gates are used.

Due to the nature of these complex processes, process control becomes critical. Monitoring systematic and random defectivity is paramount to ensure the process is within the tolerance to have yielding chips. Logic fabrication manufacturing sites (fabs) typically have product chips which consist of logic blocks and memory blocks. While the memory blocks are typically repeating array structures, the logic blocks can comprise of custom routing which lead to completely new pattern hotspots or weak points. Discovering any systematic weak design locations and providing feedback to process teams is a common practice fabs do to fix the problems inline [1,2]. During yield learning, it’s critical to ensure any weak patterns in design print reliably and can be monitored inline. Traditionally, CD-SEM can be leveraged in case the failing location is few in count. However, if the feature is not a consistent failure, it might be impractical to rely on a few patterns using CD-SEM. Litho hotspots can be anywhere from hundreds in count per chip to millions, depending on the design of the chip. In such cases, patterned wafer inspection tools are used to detect the defects inline.

Typically, there are two categories of patterned inspection tools – optical and electron-beam. Since electron-beam tools are not as fast as optical tools, getting a full wafer readout is not practical. For optical tools, there are, in general, two types of platforms: one using a narrowband laser as the illumination source, and the other using a broadband light bulb as an illuminating source. KLA-Tencor’s optical patterned wafer inspector, the 29xx Broadband Plasma (BBP) tool, uses a high intensity, laser pumped plasma light source with selectable wavelength bands [4] that can monitor different process levels on complex film stacks. The tool also enables inspecting logic blocks with enhanced sensitivity by placing design guided care areas which reduce the noise around the critical patterns significantly, thereby enhancing detection of the defect. This design based inspection is referred to as NanoPointTM capability on the tool. Various papers [1,2,3,4] discuss the ability of NanoPoint to monitor and help control design hotspots reliably.

The rest of the paper discusses the problem implementing NanoPoint care areas in production for an HVM solution, the methodology tested and results.

Developing care area strategies based on design enables the BBP tool to inspect locations which have lower noise compared to other noisier areas. Design based care areas are typically created within the design environment of the fab. There are multiple ways to generate design care areas – for example, cell search, pattern search, feedback from OPC / Litho hotspots and rule based care areas. Typically, pattern search and cell search are methods which feedback known issues after learning about the critical patterns from other sources like failure analysis (FA). These techniques can be used for focusing on critical cells to inspect like scan-chains, etc. The problem with this methodology is that while it’s optimized to focus on the key areas of the functional design, it’s not optimized for inspection of what the optical tool sees.

Rule Based Care Areas are generally used for discovering new hotspots not predicted by OPC / Litho simulations. Creating rules for a specific design requires knowledge of the design variables like spacing between lines, minimum and maximum thickness of the lines, etc. The rules are created using standard verification rule format (SVRF) or Physical Verification System (PVS). Typically, SVRF [6,7] is used for design rule check (DRC) and other purposes. However, the same syntax is used for creating care areas. An example SVRF syntax for creating care areas wherever the current layer on the design exists is shown in Text Box 1. Metal1 is the design layer of the first metal level. Active_temp01 variable grows the design by a variable called CAB (care area border). This enables the creation of care areas on the inspection tool while taking into account the ability of the optical inspector to inspect the design. Care areas can be created by using different types of rules, such as dense thin lines, Tip-to-Tip, etc.

Each mask layer in the design has different designs which leads to different requirements for care areas. Inspection-wise care areas need to be created for each layer to be inspected. Further, different customer tape-outs have different designs, which leads to different hotspots, thus causing a cumbersome care area strategy.
Maintaining care areas for each mask level for each product is cumbersome, especially, in case of >5 tape-outs. Since it’s valuable to get higher sensitivity using design based care areas, it’s paramount to create a methodology to have simple, scalable design based care areas which can support multiple design levels and also support scalability to any design for a given design rule.

Text Box 1: SVRF Rule for creating “Active” care areas.


A. Optimizing sensitivity in different regions
In front-end of line (FEOL), typically, the process starts with designing fin and STI areas followed by gates to form a transistor. Depending on design rule, the number of masks used to form a complete chip can range anywhere from 20 – 60. Having care areas for each mask level is cumbersome, but the assumption that a working transistor circuit needs both fin and gate areas simplifies creation to a single care area for all of FEOL.

Figure 1 shows an example for FEOL care area. The design is shown in yellow for gate pattern and pink for fin pattern. The translucent colors represent the care areas or “Threshold regions” denoted by the index seen on the right. There are 5 regions for inspection sensitivity. This means inspection recipe will run each care area with its own noise floor and optimize defect detection differently for different region. Array runs cell to cell inspection to maximize sensitivity for repeating patterns. PF (picture frame) runs the edge of SRAM as typically this area is noisier than the center of SRAM and prone to process systematics in early R&D. The DENSE care area covers minimum pitch logic blocks comprising of gate and fin structures. From the inspection tool, an optical image of the minimum pitch fin and gate structures are typically uniformly dark gray level and low noise compared to the rest of a chip, where open areas and sparse structures are brighter and more variable gray level with higher noise. Therefore, a care area designed to cover minimum pitch structures will also approximate the quiet dark region with maximum inspection sensitivity for capturing small defects of interest. The SPARSE care area is designed to cover the highest noise regions of the chip, such as non-critical structures like FILL areas, Blank areas, Fat gates, floating active areas (non-transistor blocks), Device Guard Rings, etc. These blocks typically are large design rule and the transitions of these structures may lead to systematic defects which are not yield-limiting. The fail mechanisms in this region which actually affect yield are typically much larger and therefore easy to detect. Therefore, this region runs at a different sensitivity during inspection. Finally, the ACTIVE care area is the region which covers everything else, in other words, design relevant care areas which are non-dense and non-sparse, covering transition areas, edges of dense blocks.

Figure 2 shows an example of BEOL care area. In this example, a bidirectional minimum pitch metal 1 (M1) design is illustrated in white. The same translucent colors in figure 1 are re-used for DENSE, SPARSE and ACTIVE care areas. DENSE covers minimum width and minimum space metal lines. SPARSE covers fat metal lines, and ACTIVE covers everything which is neither DENSE nor SPARSE.

In this work, we characterized what pitches should be used as an input to the DENSE care area region, maximizing the inspect-able area, while minimizing the gray level variation within that region so that maximum sensitivity to small defects is possible. Various design-of-experiments (DOE) were performed for both FEOL and BEOL. For FEOL care areas, a combination of fin width, gate width and fin space, gate space together needs to be analyzed. For the purposes of the study we fix the gate width/space because there is not a great deal of variation across the dense logic blocks. Typically, all dense logic is already designed with minimum gate pitch (pitch refers to 1 minimum gate width and gate space). The pitch of interest for fin is actually the NFET and PFET width and NFET-PFET space, since logic blocks are typically comprised of alternating NFET and PFET devices, composed of one to five fins each. For BEOL care areas the pitch analyzed is simply metal line width and space.

Figure 1: Scalable Care Area strategy for FEOL care areas . Design pink in color is fin and yellow is gate.

Figure 2: Scalable Care area for Mx Design (shown M1). M1 is white in color.

The metric used to quantify which combination leads to best sensitivity was defined to be the range of the variation in gray levels in each care area when inspected on the wafer. If the variation is under hundred gray levels, noise floors are similar which leads to dense region being having maximum coverage of “dense” patterns without loss of inspection sensitivity. Figure 3 illustrates that sensitivity of catching defects is proportional to gray level of the detected defect. As seen in the figure, the number of defects detected in darker or “dense” areas are fewer and are less noisy compared to areas which are brighter or “sparse”. Figure 4 illustrates a normalized graph of gray level variation as a function of pitch for DENSE threshold. For FEOL, the pitch is NFET to PFET space, and for BEOL, the pitch is metal line width/space. Figure 4 shows noise increases as more area gets added with higher pitch multipliers for DENSE region. Figure 4 represents that if DENSE only consists of 1x design rule care areas, there is much less noise and low gray level (GL) variation which leads to the highest sensitivity for catching DOI’s. As bigger Designs are added to the same care area, it becomes noisier, resulting in higher GL variation, which leads to reduced detection of the DOI’s.

Figure 3: Sensitivity as a function of noise and gray level.

Figure 4: Gray Level variation is inversely proportional to capture rate.

B. Handlingmultipleproducts/layersinagivendesignrule
Since the created care area strategy is approximated for inspection to be a function of gray level of the tool, the design multipliers used were coded in a script file which can operate on any given design file (in OAS format or GDS format) to create the five region care area strategy for FEOL or BEOL care areas. This implies that irrespective of any new design provided for a new tape-out, the care areas can be created by running a single script file which consumes the design and creates inspection-ready care areas. The sensitivity settings from the previous device which runs each region with its own sensitivity can be copied for the new device as well, thereby, automating inspection recipe setup for any new device tape-out. This methodology, leads to a consistent care area strategy which leads to a consistent inspection recipe setup for a given design rule in a production scenario.

Fig. 5: The number of care areas and time comparison for care areas per device.

Figures 5 illustrate the results of reduction in number of care areas created for one device for a 1x design rule. For FEOL care areas, each critical mask step is used for creating care areas in POR methodology leading to 22 care areas which need to be inspected. If FEOL care areas are combined using Gate and Active block approach, only 9 care areas are needed for critical inspection step monitoring. This leads to easier management of care areas.

Figure 6 shows the graph comparing care area setup using design for each new product (POR methodology) versus scalable care areas. As seen in the figure, time to results is considerably reduced leading to better efficiency and consistency for inspection recipe setup.

Fig. 6: Time comparison as a function of a new device coming per design.

It was found that, with this methodology, for a given technology node, care area creation is independent of the design itself, so can be scalable to any number of tape-outs. Using this methodology results in automating the care area generation flow. This leads to faster time to results, better efficiency for application engineers and consistent sensitivity for cross product defectivity analysis in HVM scenarios. Future work includes implementing this strategy for smaller DR’s.

The authors would like to thank Hoang Nguyen and Sumanth Kini for helping drive this project.

[1] A. Srivastava, H. Nguyen, T. Herrmann, R. Kirsch and R. M. Kini, “In- Line Inspection of Hotspots and Monitoring Strategies,” in IEEE Transactions on Semiconductor Manufacturing, vol. 29, no. 4, pp. 299- 305, Nov. 2016.
[2] D. Van den Heuvel et al., “Process window discovery methodology development for advanced lithography,” 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 2016, pp. 65-71.
[3] M. Daino et al., “Line end voids defectivity improvement on 64 pitch Cu wire interconnects of 14 nm technology,” 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 2016, pp. 60-64.
[4] A. Srivastavaet al., “Non-traditional inspection strategy for inline monitoring in excursion scenarios: Defect inspection,” 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 2016, pp. 197-200.
[5] I. Tolle, A. Jain, M. Plihal and S. Kini, “Novel methods for SPC defect monitoring: Normalizable diversity sampling: Defect inspection,” 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 2016, pp. 83-86.
[6] S. Laurent, “Physical verification of microelectronics “mask patterns” with calibre SVRF rule files,” International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., Tunis, 2006, pp. 91-93.
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As published in the Proceedings of the SEMI Advanced Semiconductors Manufacturing Conference (ASMC 2016), May 16-19, 2016, Saratoga Springs, New York.

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