Challenges In IP Reuse


Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

Wanted: More Fab Tool Part Standards


As chipmakers ramp up the next wave of processes and grapple with how to reduce defect levels, they are encountering problems from an unlikely source—components inside of the fab equipment. Defects are unwanted deviations in chips, which impact yields and device performance. Typically, they are caused by an unforeseen glitch during the process flow. But a lesser-known problem involves defe... » read more

Finding Defects In Chips With Machine Learning


Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. A subset of artificial intelligence (AI), machine learning has been used in computing and other fields for decades. In fact, early forms of machine learning ha... » read more

Reliability Becomes The Top Concern In Automotive


Reliability is emerging as the top priority across the hottest growth markets for semiconductors, including automotive, industrial and cloud-based computing. But instead of replacing chips every two to four years, some of those devices are expected to survive for up to 20 years, even with higher usage in sometimes extreme environmental conditions. This shift in priorities has broad ramificat... » read more

Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process


By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in t... » read more

3D NAND Flash Wars Begin


3D NAND suppliers are gearing up for a new battle amid a period of price and competitive pressures, racing each other to the next technology generations. Competition is intensifying as a new player enters the 3D NAND market—China’s Yangtze Memory Technologies Co. (YMTC). Backed by billions of dollars in funding from the Chinese government, YMTC recently introduced its first 3D NAND techn... » read more

More Sigmas In Auto Chips


The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Testing Cars In Context


The choices for companies developing systems or components that will work in autonomous vehicles is to road test them for millions of miles or to simulate them, or some combination of both. Simulation is much quicker, and it has worked well in the semiconductor world for decades. Simulating a chip or electronic system in context is hard enough. But simulating a system of systems in the real... » read more

Innovative Scalable Design-Based Care Area Methodology For Defect Monitoring In Production


By Ian Tolle, GlobalFoundries, and Ankit Jain, KLA-Tencor Abstract The use of design-based care areas on inspection tools [1, 2] to characterize defects has been well established in recent years. However, the implementation has generally been limited to specific engineering use cases, due to the complexity involved with care area creation and inspection recipe setup. Furthermore, creating, ... » read more

Understanding Process And Design Systematics


As design rules shrink, semiconductor manufacturing becomes more complex which leads to a huge increase in the defects which could cause a non-yielding die. Process control and inline defect analysis becomes widely relevant to help shorten the learning process from R&D to production. This paper discusses the various methodologies which leverage patterned wafer inspection tools to help analyze d... » read more

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