tag: inspection

Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process
By KLA-Tencor - 20 Sep, 2018 - Comments: 0

By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in t... » read more

The Quest For Perfection
By Ed Sperling - 10 Sep, 2018 - Comments: 0

Demands by automakers for zero defects over 15 years are absurd, particularly when it comes to 10/7nm AI systems that will be the brains of autonomous and assisted driving or any mobile electronic device. There are several reasons for this. To begin with, no one has ever used a 10/7nm device under extreme conditions for any length of time. Chips developed at these nodes are just starting to ... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Innovative Scalable Design-Based Care Area Methodology For Defect Monitoring In Production
By KLA-Tencor - 17 May, 2018 - Comments: 0

By Ian Tolle, GlobalFoundries, and Ankit Jain, KLA-Tencor Abstract The use of design-based care areas on inspection tools [1, 2] to characterize defects has been well established in recent years. However, the implementation has generally been limited to specific engineering use cases, due to the complexity involved with care area creation and inspection recipe setup. Furthermore, creating, ... » read more

Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis
By KLA-Tencor - 19 Apr, 2018 - Comments: 0

Abstract As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, ... » read more

Searching For EUV Defects
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 18 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

What’s Missing In Packaging
By Ed Sperling - 06 Nov, 2017 - Comments: 0

The growth of advanced packaging on the leading edge of design is inching backwards into older nodes. With most technology—tools, methodologies, materials and processes—this is business as usual. But in packaging, it's both counterintuitive and potentially problematic. The main reason that companies began investing in advanced packaging—OSATs, foundries, chipmakers such as Intel and Qu... » read more

Inside Panel-Level Fan-Out Technology
By Mark LaPedus - 11 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

200mm Crisis?
By Mark LaPedus - 18 May, 2017 - Comments: 7

Over the last year or so, the IC industry has experienced an acute shortage of both 200mm fab capacity and 200mm equipment amid a surge of demand for certain chips. Right now, though, the 200mm shortfall is much worse than before. But this situation isn’t expected to improve for both elements in the second half of 2017, and perhaps beyond. On the capacity front, chipmakers are generally... » read more

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