How To Catch “Disappearing” Latent Defects


Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

Challenges In Using Sub-7nm ICs In Automotive


The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

2025-Product Design Enhancement With Test Structures For Non-Contact Detection Of Yield Detractors


Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction... » read more

Nearly Invisible: Defect Detection Below 5nm


Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Using Test And Metrology Data For Dynamic Process Control


Advanced packaging is transforming semiconductor manufacturing into a multi-dimensional challenge, blending 2D front-end wafer fabrication with 2.5D/3D assemblies, high-frequency device characterization, and complex yield optimization strategies. These combinations are essential to improving performance and functionality, but they create some thorny issues for which there are no easy fixes. ... » read more

Navigating Increased Complexity In Advanced Packaging


As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Luminary Panel Sees Progress In EUV Pellicle Adoption As Critical For EUV


A significant focus of the 2024 SPIE Photomask and EUV conference was on EUV lithography and high-numerical-aperture (high-NA) EUV lithography, offering the potential to drive resolution to new heights. These EUV solutions bring new challenges such as pellicles, mask inspection, and smaller and smaller minimum mask dimensions. Progress has been impressive, according to lithography luminary Dr. ... » read more

Multi-Tier Die Stacking Enables Efficient Manufacturing


Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes require significant attention to defectivity... » read more

The Long Climb: Bringing Through Glass Vias (TGV) To High-Volume Manufacturing


The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight. The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high perfo... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs


Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

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