tag: inspection

Measuring Reflective Surfaces
By Subodh Kulkarni - 15 Jun, 2020 - Comments: 0

Manufacturers are adopting automated optical inspection (AOI) systems based on phase shift profilometry (PSP) for applications in advanced packaging processes. Many of these processes use front end-like techniques to create connections among die within a package and from the packaged die to the outside world. The technique offers fast, precise measurements of the 10µm to 100µm features that a... » read more

Using Fab Sensors To Reduce Auto Defects
By Anne Meixner - 09 Jun, 2020 - Comments: 0

The semiconductor manufacturing ecosystem has begun collaborating on ways to effectively use wafer data to meet the stringent quality and reliability requirements for automotive ICs. Silicon manufacturing companies are now leveraging equipment and inspection monitors to proactively identify impactful defects prior to electrical test. Using machine learning techniques, they combine the monitor ... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

The Convergence Of Advanced Packaging And SMT
By Subodh Kulkarni - 07 Apr, 2020 - Comments: 0

One statement is almost always true in the electronics industry: smaller is better. The relentless demand for electronic systems that pack more computing power and functionality into less space has driven the development of new processes and designs since the invention of the integrated circuit. In recent years that drive has taken a new direction, literally, as manufacturers have discovered th... » read more

How And Where ML Is Being Used In IC Manufacturing
By Mark LaPedus - 01 Apr, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

Inspection And Metrology Of Micro LED Technology
By CyberOptics - 10 Feb, 2020 - Comments: 0

Micro LEDs developed using Rohinni’s technology can be deployed in consumer electronics devices, automotive applications and outdoor signage, among other applications. The disruptive technology enables products that are brighter, thinner, lighter and more dynamic that those currently on the market, with lower power consumption than LCD or OLED. Rohinni needed an inspection and metrology so... » read more

Finding Defects In IC Packages
By Mark LaPedus - 17 Dec, 2019 - Comments: 0

Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

Using Digital Twins And DL In Lithography
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, looks at the results of inverse lithography technology at advanced nodes using curvilinear patterns, and how that can be combined with a digital twin and deep learning speed up time to market and reduce cost. » read more

Challenges Grow For Finding Chip Defects
By Mark LaPedus - 19 Sep, 2019 - Comments: 3

Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

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