tag: inspection

Macro Defect Inspection For Mission-Critical Defense, Aerospace, And Advanced R&D Fabs
By Errol Akomer - 18 Dec, 2025 - Comments: 0

Some fabs build consumer chips that sit inside phones and laptops. Others build chips that must survive in orbit, under the Arctic ice, or deep beneath the Earth’s surface. Fabs serving defense, aerospace, national laboratories, and other advanced R&D programs operate under some of the most stringent requirements in the industry. For these facilities, yield is not the only concern. Sec... » read more

Metrology Digs Deep To Produce Next-Generation 3D NAND
By Laura Peters - 09 Dec, 2025 - Comments: 1

Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace. 3D NAND technology is a core ingredient in mobile phones, solid-state dr... » read more

Operator Shortage? Intelligent Machine Vision Can Give More And Better Wafer Inspection
By Errol Akomer - 20 Nov, 2025 - Comments: 0

Right now, wafer manufacturers are having serious problems in finding and retaining operators. And they're desperately looking for ways to keep their fabs running effectively. Fortunately, machine vision can offer a smart solution. To see how it works, let’s first look at the basic fab workflow and check out some opportunities for improvement… How to improve ADI In a typical fab, after... » read more

Stop The Drip-Drip-Drip Of Intermittent In-Line Wafer Defects And Increase Your Yields
By Errol Akomer - 23 Oct, 2025 - Comments: 0

Full-blown process excursions that affect every wafer are comparatively easy for fabs to detect and fix. However, “onesie-twosie,” lower-volume excursions can go unresolved for months or even years. Some process engineers call them "slow moving excursions.” And over time, those low-volume defects can add up to significant yield losses. Ignoring a problem Some intermittent process excurs... » read more

Interconnect Innovations In High Bandwidth Memory: Part 2
By Damon Tsai - 14 Oct, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman Interconnect technology in high bandwidth memory (HBM) is at a fork in the road. One direction leads to tried-and-true microbump technology, and the other leads to a compelling alternative, hybrid bonding. Both technologies are evolving to address the stringent requirements of next generation HBM in pursuit of increased I/O density supporting high... » read more

Hybrid Approach Emerges For Edge/Cloud Inspection Of Chips
By Anne Meixner - 14 Oct, 2025 - Comments: 0

An explosion in data from inspection images and metrology measurements is creating a confusing set of demands for chipmakers and their equipment vendors. On one hand they need the massive storage and compute resources of the cloud to utilize AI/ML-based models, but they also need the faster response time of the edge to make adjustments at the tool level. Balancing these requirements is a mas... » read more

Enhancing Clip Attach Vision Accuracy In Semiconductor Manufacturing
By Mahenthren Palaniappan - 18 Sep, 2025 - Comments: 0

In the semiconductor industry, the outsourced semiconductor assembly and test (OSAT) sector plays a pivotal role in the global technology landscape. As the backbone of electronic device manufacturing, OSAT companies are entrusted with the critical task of assembly, testing, and packaging of devices. Maintaining quality in OSAT operations is of paramount importance, as it directly impacts the pe... » read more

Increasing Semiconductor Device Reliability Requires Adding More Wafer Inspection
By Errol Akomer - 18 Sep, 2025 - Comments: 0

Some industry sectors such as automotive and medical continue to push for higher and higher reliability levels; however, many fabs are having difficulties achieving them. Current inspection regimes still allow too many defects to pass through and escape to the field – primarily because of time and expense issues. Too much wafer is still left uninspected One fundamental problem is the amount... » read more

Challenges In Stacking HBM
By Ed Sperling - 03 Sep, 2025 - Comments: 1

AI data centers are pushing for higher density in high-bandwidth memory. Today, the maximum number of layers that can be stacked is 8, but that increases to as many as 24 layers by 2030. The big challenge will be in the interconnects, and making sure the microbumps align. At 16 layers, the bump pitch will be less than 10 microns, and the dies will be thinner. Damon Tsai, head of product marketi... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy