Challenges In Stacking HBM


AI data centers are pushing for higher density in high-bandwidth memory. Today, the maximum number of layers that can be stacked is 8, but that increases to as many as 24 layers by 2030. The big challenge will be in the interconnects, and making sure the microbumps align. At 16 layers, the bump pitch will be less than 10 microns, and the dies will be thinner. Damon Tsai, head of product marketi... » read more

Manufacturing At The Limits


Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

How Guardbanding Of Inline Wafer Defects Can Improve Chip Reliability Insurance


Partially defective, marginal die can still be functional enough to pass final electrical test. Some of these “walking wounded” chips get past final testing, but in the customer's end product, under ongoing stress, they may fail. This is a particularly serious issue with automotive, medical and other customers who demand maximum long-term device reliability. The semiconductor industry ha... » read more

Comprehensive Process Control Solutions For Through-Glass Vias


At some point in our lives, we have dropped a drinking glass or knocked over a glass-blown knickknack, only to watch it hit the floor and shatter into pieces. We learn from any early age that glass is fragile. But if glass is so fragile, why are manufacturers adopting glass core substrates? Good question. And one that comes with a ready answer. Glass is able to meet the new, denser line-s... » read more

Marginal Wafer Defects Can Slip Past Electrical Testing


Final electrical test remains one of the best ways to assess a circuit’s ultimate viability. But we know that, unfortunately, even 100% end-of-line electrical testing of semiconductor wafers will not guarantee that chips will not fail in the field. Certain non-killer but marginal wafer defects can still slip through electrical testing if they have sufficient electrical connectivity, even thou... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Full Wafer Inspection for Voltage Contrast Systematic Defects Using High-Throughput Point Scan


Abstract: A next generation system and methodology for high-throughput e-beam hot spot inspection is described. Rather than capturing images of each hot spot, just a single pixel centered on the signal node of each hot spot is collected and used to assess if the hot spot is defective or not. This innovation results in a very substantial savings in time per hot spot, and therefore a tremendous ... » read more

How To Catch “Disappearing” Latent Defects


Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

Challenges In Using Sub-7nm ICs In Automotive


The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

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