tag: metrology

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes
By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

X-ray Inspection Becoming Essential In Advanced Packaging
By Gregory Haley - 09 Jul, 2024 - Comments: 0

X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

Speeding Up Metrology At Advanced Nodes
By Gregory Haley - 11 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk metrology at the most advanced nodes and the impact of using different substrates, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at Onto Inn... » read more

Metrology For 2D Materials: A Review From The International Roadmap For Devices And Systems (NIST, Et Al.)
By Technical Paper Link - 30 Apr, 2024 - Comments: 0

A technical paper titled “Metrology for 2D materials: a perspective review from the international roadmap for devices and systems” was published by researchers at Arizona State University, IBM Research, Unity-SC, and the National Institute of Standards and Technology (NIST). Abstract: "The International Roadmap for Devices and Systems (IRDS) predicts the integration of 2D materials into h... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development
By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

High-NA EUVL: Automated Defect Inspection Based on SEMI-SuperYOLO-NAS
By Technical Paper Link - 10 Apr, 2024 - Comments: 0

A new technical paper titled "Towards Improved Semiconductor Defect Inspection for high-NA EUVL based on SEMI-SuperYOLO-NAS" was published by researchers at KU Leuven, imec, Ghent University, and SCREEN SPE. Abstract "Due to potential pitch reduction, the semiconductor industry is adopting High-NA EUVL technology. However, its low depth of focus presents challenges for High Volume Manufac... » read more

Progress In Wafer And Package Level Defect Inspection
By Anne Meixner - 09 Apr, 2024 - Comments: 0

The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node
By Onto Innovation - 09 Apr, 2024 - Comments: 0

DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

Using Picosecond Ultrasonics To Measure Trench Structures In SiC Power Devices
By Nick Keller - 12 Mar, 2024 - Comments: 0

The road to the future is not always a smooth, trouble-free drive. Along the way, there may be unforeseen detours, potholes and accidents, each one capable of setting progress back. But for those behind the wheel, those obstacles are just a part of the journey. Such is the case for the automotive industry as it continues to steer away from gas-powered vehicles and turn toward hybrid and elec... » read more

AI/ML Challenges In Test and Metrology
By Gregory Haley - 12 Mar, 2024 - Comments: 0

The integration of artificial intelligence and machine learning (AI/ML) into semiconductor test and metrology is redefining the landscape for chip fabrication, which will be essential at advanced nodes and in increasingly dense advanced packages. Fabs today are inundated by vast amounts of data collected across multiple manufacturing processes, and AI/ML solutions are viewed as essential for... » read more

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