Finding Defects In Chips With Machine Learning


Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. A subset of artificial intelligence (AI), machine learning has been used in computing and other fields for decades. In fact, early forms of machine learning ha... » read more

Manufacturing Bits: March 11


Measuring molecules The Technical University of Munich (TUM) has developed a new metrology technique that determines the properties of individual molecules. The technique, called single-molecule excitation–emission spectroscopy, improves upon the traditional methods to explore molecules. The traditional method, dubbed single-molecule spectroscopy (SMS), is not new and is used to analyze f... » read more

Thermal Guard-Banding


Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm. https://youtu.be/VnX-TiaMVmI » read more

A New Approach to Metrology


The startup Active Layer Parametrics Inc.'s ALPro 50 metrology tool offers “depth profiling of electrical properties at atomic-level resolution” —and automated processing with direct data transfer. The continuing miniaturization of microchips and nanochips has propelled the use of atomic-layer deposition and atomic-layer etch processes in semiconductor manufacturing. With miniaturization... » read more

New Metrology and Inspection Technologies Needed for More-Than-Moore Markets


The escalating costs of following Moore’s Law have shifted the semiconductor industry’s focus to More-than-Moore (MtM) technologies, where analog/mixed-signal, RF, MEMS, image sensing, power or other technologies may be integrated with CMOS in a variety of planar, 2.5D and 3D architectures. The integration of these and other key technologies is enabling a host of fast-growing application... » read more

In-Cell Overlay Metrology By Using Optical Metrology Tool


By Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyong Kima, Jieun Lee, DongYoung Leea, Eungryong Oh, and Ahlin Choi of SK Hynix, and Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John C. Robinson of KLA-Tencor Abstract Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced s... » read more

Digging Deep Into High Aspect Ratio Process Control For Memory Technology


By Mark Shirey and Janay Camp Data is an integral part of our lives. Contrary to the past, where files had to be removed periodically to free up storage space, we now assume that our data will never be deleted. Why risk deleting the wrong file? Just keep them! This new approach consumes a lot of memory, and intensifies the demand for storage. Two of the main workhorses of the memory segment ... » read more

Spectral Tunability For Accuracy, Robustness And Resilience


In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups a... » read more

Blog Review: July 4


Applied Materials' Sundeep Bajikar argues that to get the full benefits of AI, new computing architectures are needed – and that will require new breakthroughs in materials engineering to get beyond classic 2D scaling. Cadence's Tom Wong considers to what extent chip dis-integration is happening and how the industry can cope with the escalating costs of new process nodes and higher-speed i... » read more

Big Trouble At 3nm


As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

← Older posts