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Forksheet FET

A transistor type with integrated nFET and pFET.


Forksheet FETs are currently in development for 2nm. They fall under the gate-all-around category.

In forksheet FETs, both nFET and pFET are integrated in the same structure. A dielectric wall separates the nFET and pFET. This is different from existing gate-all-around FETs, which use different devices for the nFETs and pFETs.

Forksheet FETs allow for a tighter n-to-p spacing and reduction in area scaling. Imec’s 2nm forksheet has a 42nm contacted gate pitch (CPP) and a 16nm metal pitch. In comparison, nanosheets have a 45nm CPP and 30nm metal pitch.

Imec proposed the forksheet FET in late 2019. The proposed design included scaling boosters such as buried power rails and wrap around contacts.

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