Knowledge Center
Knowledge Center

Wide I/O: memory interface standard for 3D IC

3D memory interface standard


Wide I/O is a memory interface standard for 3D IC produced by JEDEC (JESD229). The basic concept is to use a very large number of pins, each of which is relatively slow but low powered. These concepts would not be possible for a PCB type of interconnect because of the pin limitations of those environments and the power and signal integrity issues associated with passing signals across a PCB. With stacked dies, the number of interconnects becomes a lot larger because they are not limited to the periphery of the device. In addition, distances can be less than track lengths across chip, instead being between thin die stacked vertically (50-100um). This reduces capacitance and thus power consumption.
This interface was first standardized by JEDEC in January 2012 It specifies 4 128-bit channels to DRAM running at 200MHz using single data rate technology. It produces a total bandwidth of 100Gb/S

Wide I/O 2 Aug 2014

Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.

The standard defines interfaces for 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity.