Knowledge Center
Knowledge Center

IEEE 1838: Test Access Architecture for 3D Stacked IC

Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits


Test is an important aspect of the chip fabrication process that ensures that only working die finish up in the final product. Due to the rising costs associated with test, additional logic has been placed on the chip to enable more complete test and to reduce the time that a chip has to spend on the tester. Different parts of a chip may use very different strategies for test. Examples include integrated memory test and repair capabilities, scan circuitry for logic verification and calibration circuitry for analog components.
The standard that is currently being developed will define test access features for a die that enable the transportation of test stimuli and responses both for testing of itself and its inter-die connections, as well as for testing other dies in the stack and their inter-die connections.

The proposed standard is based on, and will work with, digital scan-based test access and they plan to leverage existing test access ports (such as IEEE Std 1149.x) and on-chip design-for-test (such as IEEE Std 1500) and design-for-debug (IEEE P1687) infrastructure wherever applicable and appropriate.

Design and Modeling for 3D ICs and Interposers: 2 (WSPC Series in Advanced Integration and Packaging)

Vertical 3D Memory Technologies

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Designing TSVs for 3D Integrated Circuits (SpringerBriefs in Electrical and Computer Engineering)