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3D IC: Opportunities, Challenges, And Solutions

Like cities, chips need to go vertical to expand.

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Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as well. Chip developers can no longer count on increased density and speed from frequent process shrinks and smaller transistors. Larger dies increase capacity but bring longer signal delays and may reduce yield. Expansion in two dimensions is limited, so building up is becoming a popular option.

There are several established forms of vertical integration, including 2.5D ICs, inter-die connectivity using wire bonding, flip-chip technology, and stacked packages. These all have constraints that limit their value. The highest density and speed can be obtained with three-dimensional integrated circuits (3D ICs). Monolithic 3D SoCs build on multiple active silicon layers with vertical interconnects between the layers. This is an emerging technology not widely deployed yet. Stacked 3D ICs contain multiple dies stacked, aligned, and bonded in a single package, using through-silicon vias (TSVs) and hybrid bonding techniques for inter-die communication. Stacked 3D ICs are in production use and should be considered as an option to larger dies or migration to expensive leading-edge nodes.

3D ICs are ideal for applications that benefit from more transistors in a given footprint. Mobile SoC is an example that benefits from transistor densification but is challenged by footprint and height constraints. Similarly, cache memory chips can be stacked on top of a processor (or vice-versa) to increase bandwidth. 3D ICs are a natural choice for applications already pushing the limits of a single die at the most advanced node. Vertical stacking provides faster interconnects and has a smaller footprint than multiple packaged chips. Splitting a design into multiple smaller dies has better yield than a single large die. Stacking heterogeneous dies provides flexibility, since different manufacturing processes and nodes can be intermixed. Finally existing chips can be reused without being redesigned for incorporation into a single die, providing cost and risk reduction.

Despite the benefits and opportunities they offer, 3D ICs introduce new challenges that must be addressed. The 3D silicon system must be architected in a more holistic way, considering the third dimension. Thinking about 3D ICs only in terms of stacking 2D chips on top of each other is insufficient. The familiar three-way optimization for power, performance and area (PPA) still applies, but it becomes optimization per cubic millimeter rather than per square millimeter. The vertical dimension must be considered in all tradeoff decisions. These tradeoffs must be made across all stages of design IP, chip package, architecture, implementation, and system analysis. Ideally, 3D IC development teams should co-design the silicon IP, chiplets and package together.

Power and thermal challenges are the biggest hurdles for many 3D IC projects. In terms of powering the design, the power density is higher for a given footprint than for traditional 2D chips. The designer must consider all stacked layers in developing the power delivery network (PDN). The top die in a 3D IC gets its power from a lower die, which gets its power from a silicon or package type interposer, which gets its power from the package. Of course, applying more power in the same footprint means that more heat must be dissipated as well. Thermal issues must be anticipated, modeled, and addressed from the early phases of architecture and design. It isn’t sufficient to perform power and thermal analysis of the individual dies in isolation using electronic design automation (EDA) point tools. These create large design feedback loops that don’t allow for convergence to an optimal solution for the best PPA per cubic mm on an aggressive schedule.

3D IC design teams need a unified platform integrating system-level signal, power, and thermal analysis into a single, tightly coupled solution. This is an example of how EDA tools must evolve to support efficient 3D IC development while meeting cubic PPA targets. As another example, traditional 2D printed circuit board (PCB) tools cannot handle 3D ICs, which integrate the package with the chip. A typical PCB may have 10,000 connections, but a complex 3D IC may have billions, far outpacing what traditional tools can handle. Existing PCB tools provide no assistance for stacking dies in an IP-optimized way. Designers need a way to assemble and visualize the complete stack.

In response to the growing interest in 3D ICs and the challenges associated with their development, Synopys has merged key concepts and innovations into a unified solution. Synopsys 3DIC Compiler solution is a platform built for 3D IC system integration and optimization. It allows developers to look at many aspects of architectural design, bringing high levels of automation to manual tasks, scaling the solution to embrace the high levels of integration from advanced packaging, and integrating signoff analysis into the design flow. 3DIC Compiler includes a suite of integrated capabilities for early power and thermal analysis. This improves design efficiency and reduces the number of design iterations to meet PPA goals. It helps designers to explore the system architecture, understand the performance of the system, determine where to insert TSVs and choose the most effective die stacking approach.

3D ICs have great potential for types of electronic products. The reduced footprint and improved power efficiency are valuable for mobile devices, Internet-of-Things (IoT) and other applications where space and power are at a premium. The ability to increase performance beyond what a single die can provide is ideal for compute-intensive applications such as high-performance computing (HPC), cloud and data centers, and artificial intelligence (AI) and machine learning (ML). 3DIC Compiler helps development teams in all these domains overcome the design challenges of 3D silicon packaging to obtain the highest performance at the lowest achievable power.



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