Toward A Software-Defined Hardware World

By Karen Heyman - 06 Jun, 2024 - Comments: 0

Software-defined hardware may be the ultimate Shift Left approach as chip design grows closer to true co-design than ever with potential capacity baked into the hardware, and greater functionality delivered over the air or via a software update. This marks another advance in the quest for lower power, one that’s so revolutionary that it’s upending traditional ideas about model-based systems... » read more

Densification Of RF Designs

By Ann Mutschler - 20 Dec, 2023 - Comments: 0

It’s challenging enough to deal with wireless signals at the 5G and 6G frequencies. But with increased density in chips crammed into smaller packages, higher power, beam forming, and MIMO, design requirements are very different than in the past. Simple parasitic extraction no longer is sufficient. Daren McClearnon, product manager for RF and microwave simulation at Keysight, talks about the n... » read more

Computational Imaging Craves System-Level Design And Simulation Tools To Leverage Disruptive AI In Embedded Vision

By Synopsys - 24 May, 2023 - Comments: 0

Image quality now relies more than ever on high computing power tied to miniaturized optics and sensors, rather than on standalone and bulky but aberration-free optics. This new trend is called computational imaging and can be used either for computational photography or for computer vision. Read this white paper to learn about market trends and promising system co-design and co-optimization ap... » read more

Energy of Computing As A Key Design Aspect (SLAC/Stanford, MIT)

By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Trends in Energy Estimates for Computing in AI/Machine Learning Accelerators, Supercomputers, and Compute-Intensive Applications" was published by researchers at SLAC/Stanford University and MIT. Abstract: "We examine the computational energy requirements of different systems driven by the geometrical scaling law, and increasing use of Artificial Intelligence or Ma... » read more

The Challenge Of Optimizing Chip Architectures For Workloads

By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

3D IC: Opportunities, Challenges, And Solutions

By Kenneth Larsen - 28 Sep, 2021 - Comments: 0

Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

5G NR Design For eMBB

By Cadence - 24 Feb, 2021 - Comments: 0

This white paper examines the design challenges for eMBB products and provides examples of how these challenges can be overcome using the co-design capabilities in Cadence AWR Design Environment software. Click here to download with registration. » read more

Low Power Still Leads, But Energy Emerges As Future Focus

By Ann Mutschler - 10 Dec, 2020 - Comments: 1

In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

A New Breed Of Engineer

By Brian Bailey - 27 Feb, 2020 - Comments: 6

The industry loves to move in straight lines. Each generation of silicon is more-or-less a linear extrapolation of what came before. There are many reasons for this – products continue to evolve within the industry, adding new or higher performance interfaces, risk levels are lower when the minimum amount is changed for any chip spin, existing software is more likely to run with only minor mo... » read more

Co-Design For The AI Era

By Buvna Ayyagari-Sangamalli - 17 Dec, 2019 - Comments: 0

Welcome to the second piece in our blog series examining how the computing industry can work in new ways to enable the AI Era. In our first blog, my colleague Ellie Yieh described the enormous opportunities and challenges facing the industry as we enter a new decade, and she offered a path for accelerating innovation—from materials to systems—based on a “New Playbook” for driving im... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: co-design