tag: PDN

Unlocking PPA Benefits of Backside Routing
By Synopsys - 10 Apr, 2024 - Comments: 0

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

3D Connection Artifacts In PDN Measurements
By Cadence - 28 Feb, 2024 - Comments: 0

Authors: Ethan Koether, Amazon; Kristoffer Skytte, John Phillips, Shirin Farrahi, Cadence; Joseph Hartman, Oracle; Sammy Hindi, Ampere Computing Inc.; Mario Rotigni, STMicroelectronics; Gustavo Blando, Istvan Novak, Samtec From a simulation stand-point, we have covered several important topics that users must consider in detail to get accurate low frequency simulation results. We investigate... » read more

Distributed Batteries Within A Heterogeneous 3D IC To Optimize Performance
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits” was published by researchers at University of Florida and Brookhaven National Laboratory. Abstract: "Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electr... » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Design Considerations For Ultra-High Current Power Delivery Networks
By Quaid Joher Furniturewala - 11 Jul, 2023 - Comments: 0

This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power from voltage-regulator modules (VRMs) throughout a load board to the package’s chip pads or wafer’s die pads. The PDN includes the VRM itself, all bulk and localized capacitance, board vi... » read more

Stitching Together A Multi-Layer PCB PDN
By Patrick Carrier - 25 May, 2023 - Comments: 0

A printed circuit board (PCB) is much like a complicated city, with a myriad of intertwined pathways for data signals and power. To meet the electric current needs of modern, high-powered integrated circuits (ICs), the power distribution network (PDN) usually consists of wide power planes on multiple layers to provide a low-resistance path for power delivery. These planes are stitched together ... » read more

Covert Channel Between the CPU and An FPGA By Modulating The Usage of the Power Distribution Network
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "CPU to FPGA Power Covert Channel in FPGA-SoCs" was published by researchers at TU Munich and Fraunhofer Research Institution AISEC. Abstract: "FPGA-SoCs are a popular platform for accelerating a wide range of applications due to their performance and flexibility. From a security point of view, these systems have been shown to be vulnerable to various attacks... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm
By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
By Technical Paper Link - 12 Apr, 2022 - Comments: 0

New research paper from ETH Zurich and others. Abstract "To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's power-delivery impedance and voltage guardband, limiting the system's maximum attainable voltage (i.e., ... » read more

Batteries Take Center Stage
By Heidi Elliott - 27 Dec, 2021 - Comments: 0

For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

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