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On-Chip Power Distribution Modeling Becomes Essential Below 7nm


Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors


New research paper from ETH Zurich and others. Abstract "To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's power-delivery impedance and voltage guardband, limiting the system's maximum attainable voltage (i.e., ... » read more

Batteries Take Center Stage


For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

3D IC: Opportunities, Challenges, And Solutions


Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

A New Vision For Memory Chip Design And Verification


Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Reducing Power Delivery Overhead


The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Chip-Package Co-Analysis Using Ansys RedHawk-CPA


Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliab... » read more

Redefining The Power Delivery Network


Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Designing SoC Power Networks


Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

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