tag: PDN

3D IC: Opportunities, Challenges, And Solutions
By Kenneth Larsen - 28 Sep, 2021 - Comments: 0

Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

A New Vision For Memory Chip Design And Verification
By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Reducing Power Delivery Overhead
By Brian Bailey - 08 Jul, 2021 - Comments: 0

The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Chip-Package Co-Analysis Using Ansys RedHawk-CPA
By Ansys - 11 Nov, 2020 - Comments: 0

Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliab... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

Power Delivery Network Verification Coverage
By Various Writers - 09 Apr, 2014 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To view this white paper, click here. » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

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