A New Vision For Memory Chip Design And Verification

Why it’s getting so difficult to develop discrete memory chips and what to do about it.


Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing lines for many products that use memory chips. The pressure for greater capacity and speed is ubiquitous; high reliability, functional safety and low power consumption are also key for many applications.

There are many drivers for the memory market. Leading-edge segments with high memory usage include artificial intelligence/machine learning (AI/ML), 5G communications, cloud computing and autonomous vehicles. The needs of these applications can be met only by continuous innovation in memory design and verification. New silicon architectures and process technologies provide powerful advantages but have exacting requirements on design and fabrication. Novel designs demand full lifecycle management spanning pre-silicon, production manufacturing, and in-field operations.

Source: Synopsys

A recent blog post discussed many of these challenges in more depth and grouped them into three broad categories: scaling, silicon reliability and memory development turnaround time (TAT). Addressing all these challenges during the memory chip design and verification process requires a great deal of innovation in electronic design automation (EDA) in addition to the chip technology itself. Of course, individual EDA tools must become faster and smarter, and there is progress being made on many fronts. However, no collection of point tools—no matter how good—can meet all the requirements for leading-edge memory chip design. EDA vendors need a comprehensive and holistic approach to solutions development covering silicon technology to systems and spanning abstract models to actual chips in the field.

To meet this need, Synopsys has embarked on a strategic initiative with a corporate-wide commitment to the memory market and particular emphasis on developing broad-based solutions through close collaborations to meet or exceed requirements and enable the success of the memory customer.

As part of this initiative, Synopsys is investing in four key areas related to memory design and verification. The first is design technology co-optimization (DTCO), a methodology to enable fast and efficient evaluation and selection of new transistor architectures, materials and other process options using power, performance, and area (PPA) design metrics. This reduces cost and shortens time-to-market in advanced process development. Applying DTCO to memory technology development accelerates the overall process, making it faster and easier to adopt new silicon technology with predictable results.

The DTCO approach ties together Synopsys TCAD tools with the Synopsys Custom Design Platform and Synopsys Fusion Design Platform to enable fast technology exploration with accurate models, early PDKs, and leaf-cell and block-level design PPA assessments before wafers are available.

The second key investment area focuses on ushering in a “shift left” approach to memory design with the objective of reducing development turnaround time (TAT) without sacrificing quality. Synopsys Custom Design Platform solutions are key enablers of the “shift left” approach providing faster simulation TAT, fast ML-driven design optimization, early parasitic and reliability awareness, and higher productivity and design TAT with layout reuse.

“Digitization” of memory design is the focus of the third investment category, with the objective of applying digital flows and methodologies to solve custom design problems in memory design. Memories are primarily designed using custom design methodologies with many individual blocks still designed and optimized by hand to meet the stringent PPA requirements. The “Digitization” approach ties Fusion Design Platform technologies in timing characterization and digital implementation to enable accurate timing and power characterization, and automated timing-driven place and route of memory blocks, accelerating memory design signoff. Integration between Synopsys Custom Design Platform and Synopsys Fusion Design Platform enables seamless and efficient co-design of custom and digital blocks. The approach also borrows from the digital realm to enable a “digital-on-top” verification flow for the full chip driving significant verification TAT improvements.

The fourth investment category is design for reliability with emphasis on delivering memory-specific innovations in full lifecycle reliability verification, multi-die system design, and silicon lifecycle management. Unified reliability analysis workflows based on Synopsys Custom Design Platform technologies enable memory-specific electrical rule checks (ERC), fast electromigration/IR drop (EMIR) analysis on full chip designs with power delivery network (PDN), functional safety analysis with ISO 26262 compliance, and fast simulation-based silicon failure analysis. Synopsys 3DIC Compiler with integration to Synopsys Custom Design Platform and Synopsys Fusion Design Platform technologies enables fast exploration and pathfinding, full design implementation, and golden signoff for 2.5D/3D memory designs. Synopsys Silicon Lifecycle Management (SLM) platform with a unified analytics database and advanced technologies enables silicon-to-design optimization with healthy design margining, fast and accurate silicon failure analysis, automated high volume manufacturing analytics for yield, quality, and throughput management insights, and in-field monitoring support for robust lifecycle management.

Synopsys’ Technology Investments Focus for Memory Design and Verification

The design and verification of memory chips grow more challenging with each new generation of technology and each new demanding application. With a corporate-wide commitment and focused technology investments, leveraging industry-leading technology platforms, Synopsys is committed to providing holistic solutions that meet the needs of the memory market and enable customer success.

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