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A New Vision For Memory Chip Design And Verification


Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Radar Wave Propagation Through Materials


This white paper focuses on electromagnetic (EM) wave propagation through materials. For radar systems, this is of interest when radar must pass through walls, or when designing radomes (cover casings for the radar system). In the process of designing a radome, you should always perform full EM simulation. However, the content of this white paper will help you to first estimate whether a radome... » read more

Innovations In High-Frequency Electromagnetic Simulation


High-frequency electromagnetic simulation has evolved from “wow, now I can see how electromagnetic fields behave” to needing to know how various EM fields interact in large, complex systems. During that time, I have been an R&D engineer and I have managed a team implementing various solver technologies. We’ve been presented with plenty of challenges as electronics have continued to pr... » read more

Best Practices For Efficient And Effective Planar EM Simulation


Designers of today’s complex, multi-featured communications products require accurate and fast electromagnetic (EM) simulation to deliver cost-effective, high-performance products to market in ever-shrinking windows of opportunity. The Cadence AWR AXIEM 3D planar method-of-moments (MoM) EM analysis simulator within the AWR software portfolio delivers the accuracy, capacity, and speed designer... » read more

Using Analytics To Reduce Burn-in


Silicon providers are using adaptive test flows to reduce burn-in costs, one of the many approaches aimed at stemming cost increases at advanced nodes and in advanced packages. No one likes it when their cell phone fails within the first month of ownership. But the problems are much more pressing when the key components in data warehouse servers or automobiles fail. Reliability expectations ... » read more

Preparing For Electromagnetic Crosstalk Challenges


By Magdy Abadir and Anand Raman Electromagnetic (EM) coupling/noise is not a new phenomenon, but increasing bandwidth and decreasing size, along with low-power demands of today’s electronic systems is making EM crosstalk a first order challenge. At clock frequency of 10GHz+ and data rate of 10Gbps+, parasitic inductance and inductive coupling that were previously safe to ignore are no long... » read more

SoC Electromagnetic Crosstalk: From A Tool Perspective


Most commercial electromagnetic (EM) solvers are limited by the size of the design that they can handle, or they may take a very large amount of time or memory to perform the task. These capacity, memory or runtime constraints often lead to dropping important details about the design and the surrounding environment, which in many cases can mask the effects of EM crosstalk, or can lead to the wr... » read more

Electromagnetic (EM) Crosstalk Analysis: Unlocking the Mystery


Ignoring electromagnetic crosstalk is highly risky and can cause significant time-to-market delays as well significant cost over runs. Most current SoC design flows fundamentally ignore inductance and EM effects, and the term “EM crosstalk analysis” may sound Greek to them. This short article provides a quick overview of the basic steps involved in doing EM crosstalk analysis as part of an ... » read more

Noise Issues At 10nm And Below


Most of the conversations below 10nm have been about lithography, materials and design constraints. But as companies push to 7nm and beyond, they are faced with a host of new challenges, including how to deal with electromagnetic crosstalk. Electromagnetic crosstalk is unwanted interference caused by the electric and magnetic fields of one or more signals (aggressors) affecting another sign... » read more

Working With FinFETs


One of the key technology trends driving semi-conductor industry is the adoption of finFET processes. As opposed to a traditional planar transistor, the finFET has an elevated channel or “fin,” which the gate wraps around. Due to their structure, finFETs generate much lower leakage power and allow greater device density. Compared to planar transistors, finFET operate at a lower voltage and ... » read more

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